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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1801 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 single-chip fax/data/voice modem features single-chip integrated fax/data/voice modem two channel sd adc and three channel sd dac supports v. 34+, v.17 and fallback modem/fax standards and v.70 dsvd adsp-21xx 34 mips dsp core with sports and idma controller 16k words data memory (ram), 20k words program memory (ram and rom), 512 byte cis ram pc97-compliant single function plug and play isa/multifunction pcmcia parallel interfaces single 16.9344 mhz clock input two analog inputs and three analog outputs eight programmable i/o pins bidirectional programmable interrupt structure three pin serial memory port interface/ice-port? emulator interface/jtag boundary scan test interface programmable gain, attenuation and mute on-chip signal filters digital interpolation and decimation analog output low pass 1 hz resolution programmable audio (handset) sample rates from 5.4 khz to 48 khz, modem sample rates from 5.4 khz to 48 khz, with 1 hz, 8/7 hz and 10/7 hz resolution 128-lead pqfp and 128-lead tqfp packages operation from single +5 v supply advanced power management functional block diagram pcm_ isa pnp_ std 9 emulator i/o 9 irqx/pcmcia ext. port 1 16 sd (15:0) 16 sa (15:0)/pcmcia ext. port 1 aen/ reg iochrdy/ wait ior iow reset 8 gp i/o 3 eeprom port 5 jtag interface single function plug and play isa/ multi- function pcmcia interface control and status registers clock generation selector sport0 adsp-21xx core 34 mips sport1 idma controller i/o mapped 16 word fifo 512 3 8 dual port cis ram 4k 3 24 program boot rom 16k 3 24 program sram 16k 3 16 data sram 5 16-bit sd adc mute/ lpf daa rcvp daa rcvn daa xmitp daa xmitn line in line out handset spkrp handset spkrn monitor spkr handset mic dsp serial port/external function port 2 16.9344 mhz xtali xtalo pdw pwdack ring daa codec engine handset codec engine monitor speaker dac engine 0, +6, +12db f s 48khz 0 to C31db 0 to +22.5db +12 to C34.5db 0, C6, C12db gn/at = gain/attenuation mic gain 20db voltage reference 5 4 9 10 msf filt v ref cmout agnd av dd dgnd dv dd 16-bit sd dac pga atten 16-bit sd adc pga 16-bit sd dac mute/ analog switch gn/at 16-bit sd dac atten/ driver AD1801 sbhe/ce2 iocs16/iois16 reset f s 48khz f s 48khz f s 48khz f s 48khz ice-port is a trademark of analog devices, inc. all other trademarks are the property of their respective holders.
AD1801Cspecifications standard test conditions unless otherwise noted temperature 25 c digital supply (v dd ) 5.0 v analog supply (v cc ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz analog output passband 20 hz to 20 khz adc fft size 2048 dac fft size 8192 v ih 2.0 v v il 0.8 v v oh 2.4 v v ol 0.4 v i oh C2 ma i ol 2 ma daa receive path min typ max units full-scale input voltage (rms values assume sine wave input, pga gain = 0 db, offset error = 0% of fs) daa receive differential input 2 v rms 4.523 5.656 6.787 v p-p resistancedaa rcv input? 40 k w capacitancedaa rcv input? 15 pf programmable gain amplifier (relative to full-scale input voltage) gain = +6 db 5.5 6 6.5 db gain = +12 db 11 12 13 db analog-to-digital converter differential dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = 0 db) 81 84 db differential dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = +6 db) 78 81 db differential dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = +12 db) 75 78 db differential thd+n (C1.0 db referenced to full scale, 0.02 % 4 khz analog output passband, f s = 12.0 khz) C80 C74 db differential signal-to-intermodulation distortion? [ccif method] C90 C80 db single-ended dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = 0 db [effectively C6 db pga gain; see below*]) 81 84 db single-ended dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = +6 db [effectively 0 db pga gain; see below*]) 78 81 db single-ended dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, f s = 12.0 khz, pga gain = +12 db [effectively +6 db pga gain; see below*]) 75 78 db single-ended thd+n (C1.0 db referenced to full scale, 4 khz 0.02 % analog output passband, f s = 12.0 khz) C80 C74 db single-ended signal-to-intermodulation distortion? [ccif method] C90 C80 db crosstalk* (daa rcv input to handset mic/line input) C80 db offset error (0 v differential analog input) pga gain = 0 db 30 100 lsbs pga gain = +6 db? 30 lsbs pga gain = +12 db? 30 lsbs *when the daa receive adc is used in a single-ended input circuit configuration, the user would apply a full-scale input of 1 v rms to rcvp and connect rcvn via a 1 m f capacitor to ground. however, this will result in an output word that is C6 db down from full scale when the pga is set for 0 d b, because the adc input sees half the signal swing compared to when the adc is driven differentially. therefore, the effective pga gain of the adc, when used single-ended, is 6 db less than when used differentially. to get a full-scale output with a 1 v rms input, the pga should be programmed for 6 db gain, which is an effective single-ended gain of 0 db. C2C rev. 0 output conditions autocalibrated 0 db attenuation 0 db output relative to full scale 16-bit linear mode 600 w daa load 1 k w handset load 10 k w line out load mute off all daa transmit and handset speaker specifications are measured differentially input conditions mic 20 db gain disabled autocalibrated C1.0 db input relative to full scale 16-bit linear mode
AD1801 C3C rev. 0 handset mic/line input path min typ max units full-scale input voltage (rms values assume sine wave input) handset mic single-ended input with +20 db gain 0.1 v rms 0.226 0.2828 0.339 v p-p handset mic single-ended input with 0 db gain 1 v rms 2.26 2.828 3.39 v p-p line single-ended input 1 v rms 2.26 2.828 3.39 v p-p resistancehandset mic input? 20 k w resistanceline input? 20 k w capacitancehandset mic, line input? 15 pf programmable gain amplifier step size (0 db to 22.5 db) (all steps tested) 1.5 db gain range span? 21.5 22.5 23.5 db analog-to-digital converter dynamic range (C60 db input, thd+n referenced to full scale, a-weighted) 70 83 db thd+n (C1.0 db referenced to full scale) 0.03 % C80 C70 db signal-to-intermodulation distortion? [ccif method] C100 C80 db crosstalk? (handset mic/line input to daa rcv input) C80 db offset error (relative to full-scale analog input, pga gain = 0 db) 400 2048 lsbs daa transmit path min typ max units digital-to-analog converter dynamic range (C60 db input, thd+n referenced to full scale, 4 khz analog output passband, output gain = 0 db, f s = 12.0 khz) 81 90 db thd+n (C1.0 db referenced to full scale, 4 khz analog output passband, 0.016 % output gain = 0 db, f s = 12.0 khz) C78.5 C74 db signal-to-intermodulation distortion? [ccif method] C90 C80 db crosstalk? (daa xmit output to handset speaker/line output) C100 C80 db total out-of-band energy? (measured from 0.555 f s to 100 khz) C60 db audible out-of-band energy? (measured from 0.555 f s to 22 khz, tested at f s = 8.0 khz) C80 db common-mode dc offset (referenced to voltage reference [cmout] output) 20 mv differential dc offset 10 50 mv programmable attenuator step size (0 db to C31.0 db) (all steps tested) 0.487 1.0 1.513 db output attenuation span? 30.487 31.0 31.513 db full-scale output voltage (rms values assume sine wave output) daa xmit differential output 2.121 v rms 5.1 6.0 6.9 v p-p output source impedancedaa xmit? <2 w external load impedancedaa xmit 600 w pin capacitancedaa xmit? 15 pf load capacitancedaa xmit? 100 pf
AD1801 C4C rev. 0 handset speaker/line output path min typ max units digital-to-analog converter dynamic range (C60 db input, thd+n referenced to full scale, a-weighted) 78 86 db thd+n (C1.0 db referenced to full scale) 0.03 % C83 C70 db signal-to-intermodulation distortion? [ccif method] C90 C80 db dac crosstalk? (handset speaker/line output to daa xmit output) C100 C80 db total out-of-band energy? (measured from 0.6 f s to 100 khz) C60 db audible out-of-band energy? (measured from 0.6 f s to 22 khz, tested at f s = 8.0 khz) C80 db handset speaker common-mode dc offset (relative to voltage reference [cmout] output) 20 mv line output common-mode dc offset (relative to voltage reference [cmout] output) 40 mv differential dc offset 10 50 mv programmable amplifier/attenuator step size (+12.0 db to C34.5 db) (all steps tested) 1.0 1.5 2.0 db output attenuation span? 43.5 46.5 49.5 db mute attenuation? C100 db full-scale output voltage (rms values assume sine wave output) handset speaker differential output 1.414 v rms 3.1 4.0 4.8 v p-p line out single-ended output (10 k w load) 0.707 v rms 1.56 2.0 2.44 v p-p output source impedancehandset speaker? <2 w output source impedanceline out? 400 600 w external load impedancehandset speaker 1 1.2 k w external load impedanceline out? 10 k w pin capacitancehandset speaker 15 pf pin capacitanceline out? 15 pf load capacitancehandset speaker? 100 pf load capacitanceline out? 100 pf monitor speaker path min typ max units digital-to-analog converter thd+n (referenced to full scale) 0.316 1.0 % C50 C40 db dynamic r ange (C60 db input, thd+n referenced to full scale, a-w eighted) 50 db programmable attenuator step size (0 db, C6 db, C12 db) (all steps tested) C6.513 C6 C5.487 db output attenuation span? C12.513 C12 C11.487 db mute attenuation? C80 db full-scale output voltage (rms values assume sine wave output) monitor speaker o utput 0.707 v rms 1.7 2.0 2.3 v p-p output source impedanceCmonitor speaker? <1 w external load impedancemonitor speaker? 8 w pin capacitancemonitor speaker? 15 pf load capacitancemonitor speaker? 100 pf
C5C rev. 0 AD1801 digital decimation and interpolation filtersmodem mode 0? min typ max units passband edge (C0.220 db point) 0 0.445 f s hz passband (C3.0 db point) 0 0.490 f s hz passband ripple 0 C0.17 db transition band 0.445 f s 0.555 f s hz stopband edge 1 0.555 f s hz stopband rejection (plus 3 db rolloff) 78.0 db group delay 19/f s s group delay variation over passband 0.0 m s sample rate 48 khz digital decimation and interpolation filtersmodem mode 1? min typ max units passband edge (C0.24 db point) 0 0.400 f s hz passband (C3.0 db point) 0 0.453 f s hz passband ripple 0 C0.24 db transition band 0.400 f s 0.555 f s hz stopband edge 2 0.555 f s hz stopband rejection (plus 3 db rolloff) 52.8 db group delay 10/f s s group delay variation over passband 0.0 m s sample rate 48 khz digital decimation and interpolation filtersaudio mode? min typ max units passband edge (C0.18 db point) 0 0.400 f s hz passband (C3.0 db point) 0 0.462 f s hz passband ripple 0 C0.18 db transition band 0.400 f s 0.600 f s hz stopband edge 3 0.600 f s hz stopband rejection (plus 3 db rolloff) 78.0 db group delay 11/f s s group delay variation over passband 0.0 m s sample rate 48 khz digital interpolation filtersmonitor speaker? min typ max units passband edge (C0.74 db point) 0 0.350 f s hz passband (C3.0 db point) 0 0.412 f s hz passband ripple 0 C0.74 db transition band 0.350 f s 0.650 f s hz stopband edge 4 0.650 f s hz stopband rejection (plus 12 db rolloff) 55.5 db group delay 10/f s s group delay variation over passband 0.0 m s sample rate 48 khz notes 1 the stopband repeats itself at multiples of 64 f s where f s is the sampling frequency. thus the modem mode 0 digital filter will attenuate to C78.0 db or better across the frequency spectrum, except for a range 0.555 f s wide at multiples of 64 f s . 2 the stopband repeats itself at multiples of 64 f s where f s is the sampling frequency. thus the modem mode 1 digital filter will attenuate to C52.8 db or better across the frequency spectrum, except for a range 0.555 f s wide at multiples of 64 f s . 3 the stopband repeats itself at multiples of 64 f s where f s is the sampling frequency. thus the audio mode digital filter will attenuate to C78.0 db or better across the frequency spectrum, except for a range 0.600 f s wide at multiples of 64 f s . 4 the stopband repeats itself at multiples of 64 f s where f s is the sampling frequency. thus the audio mode digital filter will attenuate to C55.5 db or better across the frequency spectrum, except for a range 0.650 f s wide at multiples of 64 f s . specifications subject to change without notice.
AD1801 C6C rev. 0 voltage reference min typ max units cmout 2.0 2.45 2.7 v external cmout load current? 10 m a cmout output impedance? 4 k w system specifications min typ max units system frequency response ripple? (line in to line out) 0.5 db differential nonlinearity? 1bit phase linearity deviation? 5 degrees static digital specifications min typ max units high-level input voltage (v ih ) digital inputs, except xtali 2.0 dv dd + 0.3 v xtali 3.5 dv dd + 0.3 v low-level input voltage (v il ) digital inputs, except xtali C0.3 0.8 v xtali C0.3 1.5 v high-level output voltage (v oh ) 2.4 v low-level output voltage (v ol ) 0.4 v input leakage current (go/nogo tested) C10 10 m a output leakage current (go/nogo tested) C10 10 m a timing parameters (guaranteed over operating temperature and digital supply range) min typ max units reset lo pulse width (t rpwl ) 100 ns ior / iow strobe width (t stw ) 100 ns aen setup to ior / iow falling (t aesu )10ns aen hold from ior / iow rising (t aehd )0ns address setup to ior / iow falling (t adsu )10ns address hold from ior / iow rising (t adhd )0ns data hold from ior rising (t dhd1 )20ns data hold from iow rising (t dhd2 )15ns ior falling to valid read data (t rddv )40ns write data setup to iow rising (t wdsu )10ns aen iocs16 sbhe ior t aesu t aehd t rddv t dhd1 sd[0:15] sa[0:15] t adsu t adhd t stw figure 2. isa pio read cycle t cc t cc t sck t scp t scp t sch t sch t rd t rh t scdh t scdd clkout sclk dr tfs in rfs in rfs out tfs out dt tfs alternate frame mode rfs multichannel mode, frame delay 0 (mfd = 0) figure 1. serial port timing
C7C rev. 0 AD1801 power supply min typ max units power supply rangeav dd and dv dd 4.75 5.25 v power supply current5.0 av dd and dv dd operating 175 250 ma power supply current5.0 av dd and dv dd power-down 40 ma power dissipation5.0 av dd and dv dd operating (current nominal supply) 1000 mw power dissipation5.0 av dd and dv dd power-down (current nominal supply) 200 mw power supply rejection (100 mv p-p signal @ 1 khz)? (at both analog and digital supply pins, for adc and dac) 40 db clock specifications? min typ max units input crystal/clock frequency 16.9344 mhz input clock duty cycle (when an external clock is used instead of a crystal) 25/75 75/25 % initialization sample rate change time ( neglecting pipeline delay of ? 1/4 sample period) 0ms ?guaranteed, not tested. specifications subject to change without notice. aen iocs16 sbhe iow t aesu t aehd t wdsu t dhd2 t adsu t adhd sd[0:15] sa[0:15] t stw figure 3. isa pio write cycle
AD1801 C8C rev. 0 absolute maximum ratings* the AD1801 analog and digital power pins (av dd and dv dd ) must be powered by the same supply. the analog and digital power pins must always be at the same dc potential, or the AD1801 could be permanently damaged. min max units power supply digital (v dd ) C0.3 6.0 v analog (v cc ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 av dd + 0.3 v digital input voltage (signal pins) C0.3 dv dd + 0.3 v ambient temperature (operating) 0 +85 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package characteristics typ units pqfp q ja (thermal resistance [junction-to-ambient]) 35.9 c/w pqfp q jc (thermal resistance [junction-to-case]) 8.38 c/w tqfp q ja (thermal resistance [junction-to-ambient]) 36.1 c/w tqfp q jc (thermal resistance [junction-to-case]) 3.81 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1801 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description options* AD1801js 0 c to +85 c 128-lead pqfp s-128a AD1801jst 0 c to +85 c 128-lead tqfp st-128 AD1801jst-reel 0 c to +85 c 128-lead tqfp st-128 tape and reel *s = plastic quad flatpack; st = thin quad flatpack. warning! esd sensitive device
AD1801 C9C rev. 0 pin configuration s-128a 128-lead pqfp hspkrn sd7 sd8 sd9 dgnd dgnd ior iow iochrdy/ wait irq4/ inpk irq3/vctl1/ extrd irq5/ chg irq7/ spkr dv dd irq9/ ireq irq10/ cs 1 dv dd dgnd irq11/ rs 1 irq12/pd1 iocs16/iois16 sd0 sd1 dv dd dgnd sd2 sd5 dv dd dgnd irq15/vctl2/ extwr sd3 sd4 sd6 cmout lout rcvp rcvn xmitp xmitn hspkrp mspkr agnd msf av dd av dd agnd pcm_ isa pnp_ std reset reset ereset dv dd dv dd elin eint eclk ebr ee ebg ems io7 elout io6 io5 io3 io2 sd15 sd14 io0 sen sdata sck dgnd dv dd ring dgnd xtalo xtali dv dd dr/int2 sclk dgnd dv dd sd13 sd12 sd11 sd10 aen/ reg sa13/ we io4 filt agnd v ref lin mic pdw tms tdi tck tdo dv dd dgnd sa0 sa1 trs pwdack dt/pd2 sa2 sa3 sa4 sa5 sa6 av dd sa7 sa8 sa9 sa10 sa11 sa14/int1 sa15/ce1 sbhe/ce2 sa12/ oe rfs/ cs 2 tfs/ rs 2 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 100 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 56 57 58 59 55 50 51 52 53 54 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier AD1801js top view (not to scale) (pins down) io1 agnd av dd agnd
AD1801 C10C rev. 0 pin configuration st-128 128-lead tqfp 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 100 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier sd7 sd8 sd9 dgnd dgnd ior iow iochrdy/ wait irq4/ inpk irq3/vctl1/ extrd irq5/ chg irq7/ spkr dv dd irq9/ ireq irq10/ cs 1 dv dd dgnd irq11/ rs 1 irq12/pd1 iocs16/iois16 sd0 sd1 dv dd dgnd sd2 sd5 dv dd dgnd irq15/vctl2/ extwr sd3 sd4 sd6 cmout trs lout rcvp rcvn xmitp xmitn agnd hspkrn av dd mspkr hspkrp agnd msf av dd av dd agnd pcm_ isa pnp_ std reset reset ereset dv dd dv dd elin eint eclk ebr ee ebg ems io7 elout io6 io5 io3 io2 io1 sd15 sd14 io0 sen sdata sck dgnd dv dd ring dgnd xtalo xtali dv dd pwdack dr/int2 dt/pd2 sclk dgnd dv dd sd13 sd12 sd11 sd10 aen/ reg io4 filt av dd agnd v ref lin mic pdw rfs/ cs 2 tms tdi tck tdo dv dd dgnd sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sbhe/ce2 tfs/ rs 2 agnd AD1801jst top view (not to scale) (pins down) sa13/ we sa14/int1 sa15/ce1 sa12/ oe sa10 sa11
AD1801 C11C rev. 0 pin function descriptions device configuration signals pin name pqfp tqfp i/o description pcm_ isa 18 18 i pcmcia or isa host pc bus select control. this pin has a weak internal pull-up device. see below for more information. pnp_ std 19 19 i pnp or standard mode select control. when the AD1801 is configured in pcmcia mode (i.e., when the pcm_ isa pin is hi), then the pnp_ std pin can be used as a general purpose input. the pnp_stdz register bit can be used to monitor the state of this general purpose input under those conditions. this pin has a weak internal pull-up device. see below for more information. dsp core ice-port emulator interface pin name pqfp tqfp i/o description ee 29 29 i emulator enable. ebr 28 28 i emulator bus request. ebg 30 30 o emulator bus grant. ereset 22 22 i emulator reset. ems 31 31 o emulator memory select. eint 26 26 i emulator interrupt. eclk 27 27 i emulator clock. elin 25 25 i emulator input. elout 32 32 o emulator output. ring indicator pin name pqfp tqfp i/o description ring 46 46 i phone ring indicator. i/o port pin name pqfp tqfp i/o description io7 33 33 i/o/z dsp controlled programmable i/o bit 7. this pin has a weak internal pull-up device. see below for more information. io6 34 34 i/o/z dsp controlled programmable i/o bit 6. this pin has a weak internal pull-up device. see below for more information. io5 35 35 i/o/z dsp controlled programmable i/o bit 5. this pin has a weak internal pull-up device. see below for more information. io4 36 36 i/o/z dsp controlled programmable i/o bit 4. this pin has a weak internal pull-up device. see below for more information. io3 37 37 i/o/z dsp controlled programmable i/o bit 3. this pin has a weak internal pull-up device. see below for more information. io2 38 38 i/o/z dsp controlled programmable i/o bit 2. this pin has a weak internal pull-up device. see below for more information. io1 39 39 i/o/z dsp controlled programmable i/o bit 1. this pin has a weak internal pull-up device. see below for more information. io0 40 40 i/o/z dsp controlled programmable i/o bit 0. this pin has a weak internal pull-up device. see below for more information. serial memory (eeprom) port pin name pqfp tqfp i/o description sck 43 43 i/o/z serial data clock. this pin has a weak internal pull-up device. see below for more information. sen 41 41 i/o/z serial data enable control. this pin has a weak internal pull-up device. see below for more information. sdata 42 42 i/o/z bidirectional serial data. this pin has a weak internal pull-up device. see below for more information.
AD1801 C12C rev. 0 isa interface/pcmcia interface pin name pqfp tqfp i/o description sd15 58 58 i/o/z system data bus bit 15. sd14 59 59 i/o/z system data bus bit 14. sd13 62 62 i/o/z system data bus bit 13. sd12 63 63 i/o/z system data bus bit 12. sd11 64 64 i/o/z system data bus bit 11. sd10 65 65 i/o/z system data bus bit 10. sd9 67 67 i/o/z system data bus bit 9. sd8 68 68 i/o/z system data bus bit 8. sd7 69 69 i/o/z system data bus bit 7. sd6 70 70 i/o/z system data bus bit 6. sd5 73 73 i/o/z system data bus bit 5. sd4 74 74 i/o/z system data bus bit 4 sd3 75 75 i/o/z system data bus bit 3. sd2 76 76 i/o/z system data bus bit 2. sd1 79 79 i/o/z system data bus bit 1. sd0 80 80 i/o/z system data bus bit 0. sa11 104 104 i system address bus bit 11. sa10 105 105 i system address bus bit 10. sa9 106 106 i system address bus bit 9. sa8 107 107 i system address bus bit 8. sa7 108 108 i system address bus bit 7. sa6 109 109 i system address bus bit 6. sa5 110 110 i system address bus bit 5. sa4 111 111 i system address bus bit 4. sa3 112 112 i system address bus bit 3. sa2 113 113 i system address bus bit 2. sa1 114 114 i system address bus bit 1. sa0 115 115 i system address bus bit 0. ior 97 97 i system i/o read strobe. iow 96 96 i system i/o write strobe. pin name pqfp tqfp i/o isa description pcmcia description iocs16 / iois16 81 81 o/z system 16-bit i/o card system 16-bit i/o card indicator. indicator. sa12/ oe 103 103 i system address bus bit 12. system attribute space read control. sa13/ we 102 102 i system address bus bit 13. system memory space write control. sa14/int1 101 101 i system address bus bit 14. function 1 interrupt request. sa15/ ce1 100 100 i system address bus bit 15. system card enable 1. sbhe / ce2 99 99 i system byte high enable. system card enable 2. aen/ reg 98 98 i system address valid indicator. system attribute space select. irq9/ ireq 88 88 o/z system interrupt request system interrupt request/ready in dicator. mapped to irq9. iochrdy/ wait 95 95 o/z system bus cycle system bus cycle extension control. extension control. irq3/vctl1/ 94 94 o/z system interrupt request reflects the opposite state of extrd mapped to irq3. pcmcia cor1 register bit 3. cor1 bit 3 defaults as 0, so this pin defaults as hi. read strobe for interfacing to external functions, such as the smc91c94. see below for more information. irq4/ inpk 93 93 o/z system interrupt request system read cycle acknowledgment. mapped to irq4. irq5/ chg 92 92 o/z system interrupt request system status bit. mapped to irq5. irq7/ spkr 91 91 o/z system interrupt request digital audio binary waveform mapped to irq7. for driving hosts loudspeaker.
AD1801 C13C rev. 0 isa interface/pcmcia interface (continues) pin name pqfp tqfp i/o isa description pcmcia description irq10/ cs 1 87 87 o/z system interrupt request function 1 chip select. mapped to irq10. irq11/ rs 1 84 84 o/z system interrupt request function 1 reset. mapped to irq11. irq12/pd1 83 83 o/z system interrupt request function 1 power-down control. mapped to irq12. irq15/vctl2/ 82 82 o/z system interrupt request reflects the opposite state of pcmcia extwr mapped to irq15. cor2 register bit 3. cor2 bit 3 defaults as 0, so this pin defaults as hi. write strobe for interfacing to external functions, such as the smc91c94. see below for more information. reset signals pin name pqfp tqfp i/o description reset 20 20 i isa bus reset. reset is active hi. the assertion of this signal will initialize the on-chip registers to their default values. reset 21 21 i power-up reset. reset is active lo. the assertion of this signal will initialize the on-chip registers to their default values. dsp serial port (sport)/external function port 2 pin name pqfp tqfp i/o sport interface external function port 2 sclk 57 57 i/o serial clock. rfs/ cs 2 54 54 i/o receive frame sync. function 2 chip select. tfs/ rs 2 56 56 i/o transmit frame sync. function 2 reset. dr/int2 53 53 i serial data receive. function 2 interrupt request. dt/pd2 55 55 o serial data transmit. function 2 power-down control. boundary scan jtag interface pin name pqfp tqfp i/o description tms 121 121 i boundary scan function mode select. this pin has a weak internal pull- up device. see below for more information. tck 119 119 i boundary scan function clock. this pin has a weak internal pull- up device. see below for more information. tdi 120 120 i boundary scan function data input. this pin has a weak internal pull- up device. see below for more information. tdo 118 118 o boundary scan function data output. trs 122 122 i boundary scan function reset. this pin has a weak internal pull-up d evice. see below for more information. trs must be connected to digital ground (dissipates a small amount of power) or to reset (recommended) to en sure reliable operation. analog signals pin name pqfp tqfp i/o description rcvp 3 3 i daa receive line input positive differential signal. rcvn 4 4 i daa receive line input negative differential signal. mic 123 123 i handset microphone mono input. this signal can be either line level or C20 db from line level. lin 124 124 i line level single-ended input. hspkrp 8 8 o handset speaker output positive differential signal. hspkrn 9 9 o handset speaker output negative differential signal. lout 2 2 o line level single-ended output. xmitp 5 5 o daa transmit output positive differential signal. xmitn 6 6 o daa transmit output negative differential signal. mspkr 11 11 o monitor speaker single-ended output.
AD1801 C14C rev. 0 crystal and power-down signals pin name pqfp tqfp i/o description xtali 49 49 i 16.9344 mhz crystal input. when using a crystal as the clock source, the crystal should be connected between the xtali and xtalo pins. this crystal should be 16.9344 mhz for the normal sampling rate range, i.e., 5.4 khz to 44.1 khz. a clock input may be driven into xtali in place of a crystal. xtalo 48 48 o 16.9344 mhz crystal output. when using a crystal as the clock source, the crystal should be connected between the xtali and xtalo pins. if a clock is driven directly into xtali, then xtalo should be left unconnected. pdw 51 51 i power-down control. pdw is active lo. pwdack 52 52 o power-down acknowledge. voltage reference pin name pqfp tqfp i/o description cmout 125 125 o common-mode voltage output. nominal 2.25 volt reference available externally for dc coupling and level-shifting. cmout should not be used where it will sink or source current. a 10 m f tantalum capacitor in parallel with a 0.1 m f ceramic capacitor is required. v ref 126 126 i voltage re ference filter. voltage reference filter point for external bypassing only. a 10 m f tantalum capacitor in parallel with a 0.1 m f ceramic capacitor is required. filter connections pin name pqfp tqfp i/o description filt 1 1 i filter. this pin requires a 1.0 m f capacitor to analog ground for proper operation. msf 13 13 i monitor speaker filter. this pin requires a 1.0 nf cap acitor to analog ground for proper operation. power supplies and no connects pin name pqfp tqfp i/o description av dd 10, 15 10, 15 i a nalog supply voltage (+5 v 5%). 16, 128 16, 128 agnd 7, 12 7, 12 i analog ground. 14, 17 14, 17 127 127 dv dd 23, 24 23, 24 i d igital supply voltage (+5 v 5%). 45, 50 45, 50 61, 72 61, 72 78, 86 78, 86 90, 117 90, 117 dgnd 44, 47 44, 47 i d igital ground. 60, 66 60, 66 71, 77 71, 77 85, 89 85, 89 116 116 pull-up resistors: pins pcm- isa , pnp_ std , io[7:0], sen, sdata, sck, tck, tdi, tms and trs have internal pull-up devices. the pull-up device consists of a weak pmos transistor that will source anywhere from 170 m a to 340 m a of current when the pin is held at 0 volts, depending on operating temperature and voltage.
AD1801 C15C rev. 0 mixed signal functional description features modem afe v.34/v.34bis modem codec (analog front-end [afe]) with 1 hz, 8/7 hz, and 10/7 hz programmable sample rates from 5.4 to 48 khz, using 64 times oversampled, single- bit sigma-delta data conversion. support for all v.34 symbol and sample rates, including 8/7 and 10/7 symbol rates from single external 16.9344 mhz dsp crystal or clock. differential analog i/o to/from modem afe for highest signal quality. programmable gain amplifier on modem receive adc input with 0 db, +6 db or +12 db gain. programmable attenuator on modem transmit dac out- put, 0 db to C31 db with 1.0 db typical step size. handset afe full featured audio/handset codec (afe) with 1 hz pro- grammable sample rates from 5.4 khz to 48 khz, using 64 times over sampled, single-bit sigma-delta data con- version. selectable 20 db gain block for condenser microphones and selectable line input. selectable line output and differential analog output to handset speaker. programmable gain amplifier on adc input, 0 db to +22.5 db with 1.5 db typical step size. programmable gain amplifier/attenuator on dac output +12 db to C34.5 db with 1.5 db typical step size and full analog mute. monitor speaker dac sixteen word dsp output fifo to minimize dsp overhead. sigma-delta dac with sample rates tied to either modem codec or handset codec. programmable attenuator on dac output with 0 db, C6 db or C12 db attenuation, and full analog mute. output buffer to drive 8 v external monitor speaker. digital functional description features adsp-2181 dsp microcomputer core: 16.9344 mhz crystal, 33.8688 mips sustained performance. internal memory: 4k 3 24 bits boot/program rom, 16k 3 24 bits of program ram, 16k 3 16 bits of data ram, and a 512 3 8 bits dual port ram for pcmcia card configu- ration (card information structure [cis]) data tables or isa plug and play (pnp) resource data. host pc bus interface option: 16-bit isa bus or 16-bit pc- mcia pc card bus. pc 97 compliant single function plug and play (pnp) option. pcmcia pc card bus interface and multifunction card configuration controller (pc card 95 multifunction compliant). pcmcia interface supports two external card function ports for interfacing to communications ics, e.g., ethernet controllers and isdn devices. five pin synchronous serial port (sport) option over the second external function port for external serial com- munications with the dsp (communication to modem and handset adc and dac are lost). internal dma controller for handling host pc program code download and data download/upload operations into and out of internal dsp memory. eight programmable i/o lines under dsp control. power management: hardware and software controlled power-down modes with ring awakening option. programmable interrupt requests.
AD1801 C16C rev. 0 digital architectural overview the AD1801 comprises a 21xx family core, 16k 16 data memory, 16k 24 program memory, 512 bytes of cis ram and 4k 24 words of boot/program rom. please refer to the adsp-2181 dsp microcomputer data sheet (analog devices publication c2041a-4-12/95) for additional information on the adsp-2181 core, memory and peripheral features, and func tions. this data sheet makes no attempt to document the ad sp-2181 core in the AD1801. figure 4 illustrates the adsp-2181 functional block diagram. figure 5 is a functional block diagram of the unique windows ? modem function of the AD1801. the dma controller inter- faces directly to the adsp-2181s internal dma (idma) port. output regs alu output regs mac timer input regs input regs data address generator #1 data address generator #2 pma bus dma bus pmd bus instruction register program sequencer bus exchange dmd bus program sram 16k 3 24 data sram 16k 3 16 byte dma controller mux 14 14 24 16 dmd bus pma bus dma bus pmd bus input regs shifter output regs input regs mac output regs input regs alu output regs r bus 16 rx rx fifo serial port 0 serial port 1 companding circuitry 5 5 internal dma port interrupts power-down control logic 2 8 3 mux programmable i/o flags 14 external address bus external data bus 16 4 24 tx fifo tx rx rx fifo tx fifo tx adsp-2181 figure 4. adsp-2181 block diagram timing & control programmable i/o dma controller isa plug and play card configuration & interface controller pcmcia pc card configuration & interface controller serial memory eeprom port cis ram mux sclk sen sdata system address bus dsp address bus system data bus dsp data bus external function port 2 external function port 1 ring io (7:0) idma bus sa (15:0) a (10:0) sd (15:0) d (15:0) synchronous serial port figure 5. AD1801 windows modem functional block diagram windows is a registered trademark of the microsoft corporation.
AD1801 C17C rev. 0 plug and play card configuration controller the AD1801 plug and play (pnp) module provides nine out- put enables to the interrupt request pins, only one of which is active after a pnp configuration session. the pnp module also determines the cards 7-bit i/o memory base address and pro- vides an internal card select signal whenever the host pc accesses an AD1801 programmable register or the general pur- pose i/o port. the pnp_ std control input can be left uncon- nected or tied hi to enable this function. the single function pnp module in the AD1801 meets microsofts pc 97 requirements. this means that it provides a minimum of seven i/o base locations and 7 interrupts as well as performing a full 16-bit i/o address decode. since in pcm- cia mode only a single interrupt request is required, all but one of the isa interrupt request pins are redefined when the AD1801 is configured for pcmcia mode. these dual function pins are listed in table i below. since pcmcia pin require- ments exceed the minimum isa requirements, two additional isa interrupt requests can be readily accommodated as is re- flected in the table. in addition, the AD1801 provides the core dsp with the means to take the pnp function off line and permit the dsp access to the pnp internal registers. this allows the dsp the option of configuring the card at power-up, effectively bypassing the pnp card configuration sequence. table i. isa irq to pcmcia signal mapping AD1801 isa bus pcmcia bus external function pin name signal signal port-1 signal irq9/ ireq irq9 ireq irq3 irq3 irq4/ inpk irq4 inpack irq5/ chg irq5 stschg irq7/ spkr irq7 spkr irq10/ cs 1 irq10 cs 1 irq11/ rs 1 irq11 rs 1 irq12/pd1 irq12 pd1 irq15 irq15 the AD1801s pnp data address is maintained in the timing & control block, and the dma controller can be used to access the pnp data from the dsps data memory without interrupting the dsp, thus stealing no more than a single dsp cycle per transfer. this is desirable since a pnp data request can occur at any time during normal operations. isa standard mode compatibility the pnp or standard mode select input, pnp_ std , is used to enable/disable the pnp logic module. it can be tied to dv dd or left unconnected to enable the pnp logic or tied to dgnd if pnp is not to be supported. an internal pull-up ensures that a hi state is seen when the pin is left unconnected. this input is available for the dsp to read. this allows the implementation of schemes that require the dsp to determine a suitable pc i/o space base address and pc interrupt for the i/o slave card when the standard mode is active. the dsp must program a 13-bit default base address register with a 13-bit i/o memory base address and a 4-bit default interrupt select register for selecting the active irq output. these registers are located in the AD1801s timing & control block and are active whenever inputs pnp_ std and pcm_ isa are tied to dgnd. adsp-2181 (dsp) interface external bus the windows modem function block interfaces to the adsp- 2181s external bus as an i/o peripheral to give the dsp access to control registers, status bits and the i/o ports. note that the physical connections for this interface are made completely i nside the AD1801. a 7-bit base address a[10:4], starting at address 0x000 (see table vii), plus a 4-bit destination address, a[3:0], is decoded inside the windows modem function. an i/o opera- tion is qualified by an active ioms signal initiated by the dsp. up to 16 bits of the dsp external data bus, d[15:0], are used for passing data into and out of the windows modem block; the direction is determined by dsp memory and enables controls rd and we . no wait states are required for internal dsp i/o operations. internal dma port the windows modem function block interfaces to the adsp- 2181s internal dma port to provide the host pc with the means to access on-chip program and data memory. this com- munications path is crucial to the operation of the AD1801; it handles back-to-back host pc read or write operations for the active bus interface, i.e., it sustains data transfers of 4.17 mbytes/s over the isa 16-bit data bus and 8 mbytes/s over the pc card 16-bit data bus. this interface consists of a 16-bit multiplexed address/data bus (iad[15:0]), port read ( ird ), write ( iwr ), address latch (ial) and start ( is ) control pins plus an acknowledge ( iack ) output. timing and control the windows modem block of the AD1801 uses the maximum 33.8688 mhz clock output generated by the dsp core from an external 16.9344 mhz source. an external power-on reset circuit or the host pc bus reset provides a reset to both the core dsp and windows modem blocks; this forces the dsp to re- boot from the internal rom, rebuild the cis table in the small internal ram, and initialize various windows modem program- mable registers. the ring input is used as one interrupt to the dsp; a second interrupt is generated in the windows mo- dem timing and control block under host pc program control. the dsp can selectively enable/disable the r ing detection inter- rupt via a bit in the dsp control register. isa platform compatible host pc the AD1801 is targeted for use in isa add-on i/o slave card designs. it provides a glueless interface to the isa bus when- ever the pcm_ isa control input is tied lo. all bus drivers are compliant with isa interface, electrical switching and drive capability specifications. in particular, fast outputs are not used as collectively they can induce glitches onto other bus controls when they are simultaneously switched. isa 16-bit data bus interface the AD1801s isa bus interface meets the timing specifica- tions defined for 16-bit data isa i/o standard access cycles. this interface consists of a 16-bit address bus (sa[15:0]), 16-bit data bus (sd[15:0]), i/o read and write strobes ( ior and iow ), hardware reset reset, iochrdy/ wait , iocs16 / iois16 , and nine inter rupt requests. one of the interru pts is selected for use by the card when it is configured; the others remain in a high impedance state to allow other cards their use. one bit in the AD1801s dsp control register serves as the interrupt request to the pc. its logic state is totally under dsp program control. a bit in the pc control register allows the host pc to disable interrupt requests.
AD1801 C18C rev. 0 pcmcia platform compatible host pc the AD1801 is also targeted for use in pcmcias pc card standard slave card designs. it provides a glueless interface to the pc card bus whenever the pcm_ isa control input is un- connected or tied to dv dd . an internal pull-up allows this pin to be left unconnected in this mode. pcmcia 16-bit pc card bus interface the AD1801s pc card bus interface meets the timing specifi- cations defined for pcmcias pc card bus standard 95 for both memory and i/o access cycles. this interface consists of a 12-bit address bus (sa[11:0]), 16-bit data bus (sd[15:0]), i/o read and write strobes ( ior and iow ), card enables ( ce1 and ce2 ), hardware reset (reset), memory read and write strobes ( oe and we ), attribute and i/o memory select ( reg ), pc interrupt/ready control ( iois16 ) and a read cycle acknowledge control ( inpk ). pcmcia card configuration controller this module supports up to three card functions. multiple function pc cards require a separate set of configuration regis- ters per function. a primary cis common to all functions plus separate secondary ciss, one per function, are also required. data for the card information structures (ciss) is loaded into the internal 512-byte cis ram by the dsp during bootstrap loading. the dsp can obtain the data it needs from both its internal rom and, for card-specific data, from an external serial eeprom. the dsp sets a control bit in the AD1801 to indi- cate that ram initialization has completed. the dsp does not have read access to the cis memory. the host pc can read the cis memory at any time. if needed, the wait control can be activated to extend the read operation to meet bus cycle timing specifications. the host pc does not have write access to the cis memory. the cards modem function is implemented primarily within the AD1801. the ring input can be used to activate the pcmcias stschg status line to notify the host pc of ring- ing on the phone line. the host pc must set the req_attnenab and sigchg bits in the AD1801s extended status register and card configuration and status register, respectively, to activate this feature. a binary audio waveform, spkr , is available for use in lieu of the aud output. this bus signal is intended to drive the hosts loudspeaker. the 1.4 mb/sec bitstream from the monitor speaker sigma delta engine provides the binary audio data stream for this pin. the host pc must set the audio bit in the card configuration & status register to enable this output. the AD1801 provides two external function ports for support- ing limited control of communications ics, such as ethernet controller and isdn devices, for example. each external func- tion port will consist of a function reset, chip select, address latch control, power-down control, and a function interrupt input. this interrupt will be passed on to the host pc if its particular function enable and interrupt enable controls are activated. the AD1801 also generates read and write strobes to facilitate data transfers between the host pc and the communi- cation ic. strobe timing is designed to meet the timing require- ments of standard microsystems corporations smc91c94 ethernet controller whenever external function 1 is accessed by the host pc. the host pcs read and write strobes will be passed through the AD1801 whenever external function 2 is accessed by the host pc. table ii identifies the pcmcia function configuration registers needed to support each card function.
AD1801 C19C rev. 0 table ii. pcmcia function configuration registers *not implemented, reads 0, writes ignored. s r e t s i g e r n o i t a r u g i f n o c n o i t c n u f s t i b d n a s r e t s i g e r d e r i u q e r e m a n t i b r e b m u n t i b e m a n m e d o m l a n r e t n i n o i t c n u f n o i t c n u f l a n r e t x e 1 - t r o p n o i t c n u f l a n r e t x e 2 - t r o p r e t s i g e r n o i t p o n o i t a r u g i f n o c7t e s e r ss e ys e ys e y 6q e r l v e l111 5n o i t p o r o d n e v000 4n o i t p o r o d n e v000 3n o i t p o r o d n e v000 2n e q e r is e ys e ys e y 1n e e s a b o / is e ys e ys e y 0n e . c n u fs e ys e ys e y r e t s i g e r s u t a t s & n o i t a r u g i f n o c d r a c7g n h cs e yo no n 6g h c g i ss e yo no n 58 s i o i00 0 4d e n i f e d t o n000 3o i d u as e yo no n 2n d r w ps e ys e ys e y 1r t n is e ys e ys e y 0k c a r t n is e ys e ys e y r e t s i g e r t n e m e c a l p e r n i p71 d v b c** * 62 d v b c** * 5y d r c* * * 4t o r p w c** * 31 d v b r** * 22 d v b r** * 1y d a e r r*** 0t o r p w r** * r e t s i g e r y p o c d n a t e k c o s7 ) 0 ( d e v r e s e r*** 6 5 t i b - 3 y p o c r e b m u n ** * 4 3 2 t i b - 3 t e k c o s r e b m u n ** * 1 0 r e t s i g e r s u t a t s d e d n e t x e73 t v e d v s r0** 62 t v e d v s r0** 51 t v e d v s r0** 4t v e n t t a q e rs e y* * 33 b a n e d v s r0** 22 b a n e d v s r0** 11 b a n e d v s r0** 0b a n e n t t a q e rs e y* * ) 4 ( s r e t s i g e r s s e r d d a e s a b o / i) 0 : 7 (0 e s a b o is e ys e ys e y ) 8 : 5 1 (1 e s a b o is e ys e ys e y ) 6 1 : 3 2 (2 e s a b o i*** ) 4 2 : 1 3 (3 e s a b o i*** r e t s i g e r e z i s o / i) 0 : 7 (e z i s o is e ys e ys e y
AD1801 C20C rev. 0 all registers in pcmcia attribute memory space (0x200 to 0x27f) will read 0 and ignore writes unless specifically documented in the sections below. table iii. pcmcia bus transaction transaction type iord iowr oe we reg i/o read 01110 i/o write 10110 attribute memory read 11010 attribute memory write 11100 ce1 data sd[15:0] d7:d0 (even byte) setup command hold addr sa[15:0] reg ce2 oe we cycle time figure 6. pcmcia attribute memory read transfer ce1 data sd[15:0] d7:d0 (even byte) setup command hold addr sa[15:0] reg ce2 oe we cycle time figure 7. pcmcia attribute memory write transfer
AD1801 C21C rev. 0 addr sa[15:1] data sd[15:0] reg a0 ce1 ce2 iord iowr iois16 wait cycle time (255 ns) d7:d0 (even byte) setup command recovery figure 8. pcmcia default read cycle addr sa[15:1] data sd[15:0] reg a0 ce1 ce2 iord iowr iois16 wait cycle time (255 ns) d7:d0 (even byte) setup command recovery figure 9. pcmcia default write cycle
AD1801 C22C rev. 0 addr sa[15:1] data sd[15:0] reg a0 ce1 ce2 iord iowr iois16 wait cycle time (255 ns) d15:d0 (word) setup command recovery figure 10. pcmcia 16-bit word i/o read cycle addr sa[15:1] data sd[15:0] reg a0 ce1 ce2 iord iowr iois16 wait cycle time (255 ns) d15:d0 (word) setup command recovery figure 11. pcmcia 16-bit word i/o write cycle
AD1801 C23C rev. 0 interrupt architecture the signals used in generating interrupts are shown in table iv. table iv. interrupt architecture pins description pcm_ isa indicates that the AD1801 is in pcmcia mode or isa mode. ring falling edge signal indicates a ring interrupt. int1 external function 1 interrupt request pin. assumed to be a level signal if intrack1 = 0. can be edge if intrack1 = 1. int2 external function 2 interrupt request pin. assumed to be a level signal if intrack2 = 0. can be edge if intrack2 = 1. pcmcia/ pnp signals description func0en in pcmcia mode, the func0en bit is the enable function bit in the configuration option register, cor0[0]. in pnp mode, the func0en bit is the active bit for logical device zero. func1en in pcmcia mode, the func1en bit is the enable function bit in the configuration option register, cor1[0]. in pnp mode, the func1en bit is deasserted. func2en in pcmcia mode, the func2en bit is the enable function bit in the configuration option register, cor2[0]. in pnp mode, the func2en bit is deasserted. intrackx pcmcia defined bit that determines the mode for clearing interrupts. when intrackx = 0, interrupts are cleared at the function (i.e., by the dsp or host writing to ack bits). when intrackx = 1, interrupts are cleared via the intr bit (csrx[1]). intrackx is csrx[0]. the assertion of any of the three intracks (from the three csr registers) will cause the entire part to behave as if all three intracks w ere asserted. reads of the intrack bits will always return what was written. intr0 csr0[1]. reads of intr0 indicate if the dsp/ring interrupt is asserted even if the interrupt pin enable 0 (ireq0en) is deasserted. intr1 csr1[1]. reads of intr1 indicate if the external function 1 interrupt is asserted even if the interrupt pin enable 1 (ireq1en) is deasserted. intr2 csr2[1]. reads of intr2 indicate if the external function 2 interrupt is asserted even if the interrupt pin enable 2 (ireq2en) is deasserted. intr0 (wr = 0) a write of 0 to the intr0 bit, csr0[1]. when intrack0 = 1, this causes both the dsp and ring interrupts to clear. when intrackx = 0, the write has no effect. intr1 (wr = 0) a write of 0 to the intr1 bit, csr1[1]. when intrack1 = 1, this causes the external function 1 (int1) inter- rupt to clear. when intrack1 = 0, the write has no effect. intr2 (wr = 0) a write of 0 to the intr2 bit, csr2[1]. when intrack2 = 1, this causes the external function 2 (int2) inter- rupt to clear. when intrack2 = 0, the write has no effect. ireq0en host writable bit (in the pcmcia control registers) that enables dsp/ring interrupts on the ireq# pin. pcmcia mode only. (created from cor0[2].) ireq1en host writable bit (in the pcmcia control registers) that enables external function 1 interrupts on the ireq# pin. pcmcia mode only. (created from cor1[2].) ireq2en host writable bit (in the pcmcia control registers) that enables external function 2 interrupts on the ireq# pin. pcmcia mode only. (created from cor2[2].) irqseln nine versions of this signal exists for each of the nine isa interrupt levels possible; assertion is mutually exclusive. irqseln signals are created from the pnp irq level register.
AD1801 C24C rev. 0 table iv. interrupt architecture (continued) dsp accessible signals description pcirq dsp writable bit to request an interrupt on the system bus. dspix dsp writable bit to acknowledge/clear the dsp interrupt. interrupt is acknowledged/cleared when dspix is set to 1. wri ting this bit has no effect when in pcmcia mode with intrack0 = 1. rngix dsp writable bit to acknowledge/clear the ring interrupt. writing this bit has no effect when in pcmcia mode with intrack0 = 1. host accessible signal (not including those in pcmcia/pnp registers) description dspie host writable bit which enables dsp interrupts. rngie host writable bit which enables ring interrupts. dspi host readable bit which indicates whether an interrupt is pending from the dsp. rngi host readable bit which indicates whether an interrupt is pending from the ring pin. dspia host writable bit to acknowledge/clear the dsp interrupt. writing this bit has no effect when in pcmcia mode with intrack0 =1. rngia host writable bit to acknowledge/clear the ring interrupt. writing this bit has no effect when in pcmcia mode with intrack0 =1. table v. dsp interrupt mapping i nterrupt source interrupt vector address comment reset 0x2000 (rom) highest priority power down 0x002c (ram) host pc (irq2) 0x0004 (ram) triggered by writing 1 to pd bit in pcc register io0 pin (irql1) 0x0008 (ram) triggered by rising or falling edge of io0 pin pcmcia power-down (irql0) 0x000c (ram) t riggered while pwrdn = 1 in csr0 or pdw pin lo sport 0 transmit 0x0010 (ram) sport 0 receive 0x0014 (ram) ring pin (irqe) 0x0018 (ram) triggered by falling edge on ring pin sport 1 transmit 0x0020 (ram) sport 1 receive 0x0024 ( ram) timer 0x0028 (ram) lowest priority
AD1801 C25C rev. 0 dma controller the AD1801s dma controller block ensures that both pro- gram code and data supplied by the host pc is loaded into on- chip memory in an efficient manner. the address counter in the i dma port can facilitate block transfers using the auto incrementing mechanism. the host pc uses two locations in its i/o memory map for transferring data to and from on-chip program/data memory. one location allows the host pc effective access to the idma control (idmac) register. this register is used by the host pc to program the 14-bit memory address counter (register bits 13:0) and 1-bit destination indicator (register bit 14). this register needs only to be programmed once for block transfers to/from the same type of memory, since the address counter is automatically incremented for each idma read/write operation. the destination indicator is programmed to a 1 whenever the host pc wishes to access data memory, otherwise program memory will be accessed. the second i/o location is reserved for the 16-bit data word provided to or supplied by the host pc. this location is mapped to a read-only memory data input (mdi) register and to a write-only memory data output (mdo) register. when accessing the 24-bit program memory, two host pc read or write cycles from mdi or to mdo, respectively, are re- quired. the first program memory access, or any odd num- bered access following an idmac register update applies to the most significant (ms) 16 bits of the 24-bit program data word (bits 23:8). the second access, or any even numbered access following an idmac register update applies to the least sig- nificant (ls) eight bits of the 24-bit program word (bits 7:0). bits mdo(15:8) are ignored by the AD1801 in this case for write operations; the host pc will receive valid data on mdi(7:0) for read operations. the idma address counter is not incremented until after the ls byte portion of the 24-bit program data word has been addressed. if the idmac register is updated before the second half of a program data read/write operation is ex ecuted, the capability to access the ls byte for the previous address value will be lost; the dma controller will access the ms 16 bits of the data at the new address during the following program memory read/write operations. when accessing data memory, only a single read or write cycle is required since the 16-bit memory words are accommodated by the dma bus, iad(15:0), and the host pc data bus, sd(15:0); however, the idmac register must be programmed first to let the dma controller know that the next host pc initiated memory access cycles are targeted for data memory and to de- fine a starting address. the idmac register is incremented upon completion of each successive write/read operation to/from the memory data registers, mdo and mdi. the dma controller is able to provide the host pc with data without use of wait states for back-to-back read and write opera- tions. the dsp continues to run at full speed while synchroni- zation is achieved over a dma bus cycle request; only then is a single dma cycle stolen from the dsp. the entire dma bus !func0en rst set clr sticky latch q dspie pcirq dspix dspia intr0 (wr=0) (pcmcia * intrack0) dspi rngie ring pin rngix rngia intr0 (wr=0) (pcmcia * intrack0) rngi !func1en !pcmcia+!intrack1 int1 pin intr1 (wr=0) (pcmcia * intrack1) !func2en !pcmcia+!intrack2 int2 pin intr2 (wr=0) (pcmcia * intrack2) intr0 intr1 intr2 ireq1en ireq2en irq3 (isa) irq4 (isa) irq5 (isa) irq7(isa) irq9 (isa) irq10 (isa) irq11(isa) irq12 (isa) irq15 (isa) irqsel3 irqsel4 irqsel5 irqsel7 irqsel9 irqsel10 irqsel11 irqsel12 irqsel15 ireq (pcmcia) 500ns delay arbiter 0 1 0 1 !func0en rst set clr sticky latch q rst set clr sticky latch q 0 1 rst set clr sticky latch q 0 1 pcmcia 0 1 ireq0en pnpirqnen figure 12. interrupt structure
AD1801 C26C rev. 0 cycle can take from 2.5 to a maximum of 3.5 dsp cycles to complete. one or two cycles are required for synchronization, then there is a half cycle setup time for the iack control, fol- lowed by the single data transfer cycle. if data cannot be presented onto the pc card bus w ithin 100 ns from the falling edge of a read strobe using either the long or short idma read cycle timing, a data prefetch mechanism for every address counter update will be required. internal holding registers can be used, essentially, to create a 1-word deep fifo or to create a word register pair employing a ping-pong access arrangement, in order to meet pc card bus timing requirements. synchronous serial port the AD1801 provides an external synchronous serial port (identical to the sport module in the adsp-2181) that can be optionally selected in place of the second external function under the pcmcia modules control. the port mode (pm) bit in the dsp control register is used to select the enable option. power-down modes the power-down control pins, pwd and pwdack, available on the adsp-2181, are brought out of the AD1801 to provide a hardware option for putting the dsp core in a low power state. the active hi pwdack control indicates when the processor is powered down; it is deactivated when the processor has completed its power-up sequence. a logic lo on this pin also indicates that the processors clkout signal is valid and that program execution has begun. general purpose i/o port the AD1801 provides eight bits of general i/o, io(7:0), that can be programmed by the dsp. the i/o port control (ipc) register determines port bit direction; a logic 0 sets a port bit to an output while a logic 1 sets a port bit to an input. each port bit is tied to an internal weak pull-up resistor. the AD1801 provides a single 8-bit output port register that is programmed by the dsp. input port bits are not registered; they are simply passed onto the dsp data bus (d[15:0]) during active read operations accessing the dsp input port. note that the dsp will read the internally generated output port bits that are active along with the active externally supplied input port bits. the e ight programmable i/o pins on the AD1801 (pins 33 through 40) will source between 170 m a and 340 m a when they are three-stated. this feature provides weak pull-up capability from power-on. this current sourcing capacity should only be used to determine how fast the AD1801 will pull up the pin and how much current devices driving the AD1801s i/o pins need to sink to drive to logic lo. when configured as outputs, the i/o pins will source 0.5 ma at 2.4 v (hi level output voltage) and will sink 2.0 ma at 0.4 v (lo level output voltage). they are conservative ratings for 10 ns edge transitions with a 50 pf load. jtag scanning logic jtag boundary scan logic is included in the AD1801. the AD1801 is compliant with ieee std. 1149.1a-1993. only the mandatory instructions are supported. these are: bypass, sample/preload, and extest. scan order, from first in to last in, as follows. table vi. jtag scan order 0 pcm_ isa 43 rfs/cs2 outen 86 irq15/vctl2 1 pnp_ std 44 rfs/ cs 2 87 irq12/pd1 outen 2 reset 45 dt/pd2 outen 88 irq12/pd1 3 reset 46 dr/pd2 89 irq11/ rs 1 outen 4 ereset 47 tfs/ rs 2 outen 90 irq11/ rs 1 5 testb (dv dd ) 48 tfs/ rs 2 91 irq10/ cs 1 outen 6 elin 49 sclk outen 92 irq10/ cs 1 7 eint 50 sclk 93 irq9/ ireq outen 8 eclk 51 sd15 outen 94 irq9/ ireq 9 ebr 52 sd15 95 irq7/ spkr outen 10 ee 53 sd14 outen 96 irq7/ spkr 11 ebg 54 sd14 97 irq5/ chg outen 12 ems outen 55 sd13 outen 98 irq5/ chg 13 ems 56 sd13 99 irq4/ inpk outen 14 elout 57 sd12 outen 100 irq4/ inpk 15 io7 outen 58 sd12 101 irq3/vctl1 outen 16 io7 59 sd11 outen 102 irq3/vctl 17 io6 outen 60 sd11 103 iochrdy/ wait outen 18 io6 61 sd10 outen 104 iochrdy/ wait 19 io5 outen 62 sd10 105 iow 20 io5 63 sd9 outen 106 ior 21 io4 outen 64 sd9 107 aen/ reg 22 io4 65 sd8 outen 108 sbhe / ce2 23 io3 outen 66 sd8 109 sa15/ ce1 24 io3 67 sd7 outen 110 sa14/int1 25 io2 outen 68 sd7 111 sa13/ we 26 io2 69 sd6 outen 112 sa12/ oe 27 io1 outen 70 sd6 113 sa11 28 io1 71 sd5 outen 114 sa10 29 io0 outen 72 sd5 115 sa9 30 io0 73 sd4 outen 116 sa8 31 sen outen 74 sd4 117 sa7 32 sen 75 sd3 outen 118 sa6 33 sdata outen 76 sd3 119 sa5 34 sdata 77 sd2 outen 120 sa4 35 sck outen 78 sd2 121 sa3 36 sck 79 sd1 outen 122 sa2 37 ring 80 sd1 123 sa1 38 xtali 81 sd0 outen 124 sa0 39 xtalo 82 sd0 40 pdw 83 iocs16 / iois16 outen 41 pwdack 84 iocs16 / iois16 42 dr/int2 85 irq15/vctl2 outen note the jtag input trs (pin 122) must be connected to digital ground (which dissipates a small amount of power due to the on-chip weak pull-up device) or to reset (recommended) to ensure reliable AD1801 operation.
AD1801 C27C rev. 0 emulation mode (ez-ice ? port) unlike the adsp-2181, which ignores its normal (non-emulator) reset pin when in emulator mode, all AD1801 reset sources are still functional when in emulator mode. this includes the reset pin (isa reset), the reset pin (power-up reset), the rst (host pc reset) bit in i/o mapped register pcc, pnp reset, and pcmcia reset. as a result, in order to avoid erroneous emula- tor results, care must be taken to prevent the assertion of any of these resets during periods of time when the emulator actually takes control of the dsp core. the 14-pin ez-ice port interface should be connected to the AD1801 as indicated below. table vii. emulator connections ez-ice connector pin AD1801 connection 1 gnd digital gnd (not analog supply) 2 bg no connect 3 ebg ebg (pin 30) 4 br digital v dd (not analog supply) 5 ebr ebr (pin 28) 6 eint eint (pin 26) 7 key no connect 8 elin elin (pin 25) 9 elout elout (pin 32) 10 eclk eclk (pin 27) 11 ee ee (pin 29) 12 ems ems (pin 31) 13 reset digital v dd (not analog supply) 14 ereset ereset (pin 22) as with the adsp-2181, all AD1801 emulation pins (pins 22 and 25C32) sho uld be floated when not connected to the ez-ice port. within the AD1801 there is a pull-down resistor on the ee (emulation enable) pin which disables emulation mode when the ee pin is floated. note that the adsp-2181 chip includes two emulator signals not found (and not required) on the AD1801 bg (bus grant) and br (bus request). under normal adsp-2181 operation, and external device can interrupt the dsp to use its bus. this is done with the br and bg pins; the external device asserts br , and the adsp-2181 asserts bg when the bus is available. in the same scenario with an ez-ice in the system, the ez-ice takes the br signal, ors in its own bus request, and generates ebr to the adsp-2181. the adsp-2181 then asserts ebg , which the emulator may pass on to the external device as bg . during emulator mode, the adsp-2181 ignores br and three-states bg (so that the emulator can drive it instead). since the AD1801 does not allow any external devices to be connected to the dsp core, there is no need for the br and bg signals. when using an emulator, br should be wired deasserted (hi) on the emulator connector. pc and dsp i/o mapped register descriptions pc i/o memory map the AD1801 bus interface uses the base address determined during an initialization period to allow host pc access to its internal registers and ports according to the table below. the base address will correspond to system address bits sa (15:3) when the AD1801 is in isa mode and to bits sa (11:3) when the AD1801 is in pcmcia mode. table viii. pc i/o memory map system address resource accessed bits sa [11:3] reads writes function base addr + 0 pcs pcc host pc status and control base addr + 2 reserved idmac internal dma address base addr + 4 mdi mdo memory data i/o base addr + 6 tm tm test mode p c attribute memory map attribute memory space is defined for pcmcia AD1801 con- figurations only. all registers in pcmcia attribute memory space (0x200 to 0x27f) will read 0 and ignore writes unless specifically documented. the AD1801 provides three pcmcia functions. function 0 is completely contained on the AD1801 chip (i.e., the fax/data/ voice modem), while functions 1 and 2 are implemented exter- nally to the AD1801 and are supported with i/o pins. table ix. pc attribute memory map system register/ram accessed address name valid operation 0x000C0x3ff cis ram read only 0x400 cor0 read/write 0x402 csr0 read/write 0x406 scr0 read/write 0x408 esr0 read/write 0x40a iobl0 read/write 0x40c iobh0 read/write 0x412 ios0 read/write 0x440 cor1 read/write 0x442 csr1 read/write 0x446 scr1 read/write 0x44a iobl1 read/write 0x44c iobh1 read/write 0x452 ios1 read/write 0x480 cor2 read/write 0x482 csr2 read/write 0x48a iobl2 read/write 0x48c iobh2 read/write 0x492 ios2 read/write ez-ice is a registered trademark of analog devices, inc.
AD1801 C28C rev. 0 pcmcia configuration option registers cor0: pcmcia function 0 configuration register access: read/write address: 0x400 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d t e s e r sq e r l v e l] 5 [ x e d n i f n o c] 4 [ x e d n i f n o c] 3 [ x e d n i f n o c] 2 [ x e d n i f n o c] 1 [ x e d n i f n o c] 0 [ x e d n i f n o c sreset function 0 software reset. setting this bit to 1 places the AD1801 in the reset state. this is equivalent to asser- tion of the hardware reset signal except that this bit is not cleared. resetting this bit to 0 leaves the AD1801 in the same state that follows a hardware reset. this bit is reset to 0 by power-up and hardware reset. this bit is sticky. levlreq function 0 level mode ireq . level mode interrupts are defined when this bit is 1. pulse mode (edge trig- gered) interrupts are defined when this bit is 0. this bit is hardcoded to 1 (level mode interrupts). confindex[5:3] configuration index bits 5 through 3 are defined as vendor specific and are not used to control anything on the AD1801. these bits can be written and read for general scratchpad purposes. confindex[2] configuration index bit 2 enables ireq routing. when set to 1, ireq interrupts are enabled for function 0. when reset to 0, ireq interrupts are disabled for function 0. this bit is valid only when confindex[0] (func- tion enable) is set to 1 (enabled). confindex[1] configuration index bit 1 specifies the i/o addressing used. when set to 1, i/o addresses specified by the base and limit registers are passed to function 0. when reset to 0, all host i/o addresses are passed to function 0. this bit is valid only when confindex[0] (function enable) is set to 1 (enabled). confindex[0] configuration index bit 0 enables or disables function 0. when set to 1, function 0 is enabled. when reset to 0, function 0 is disabled and does not decode i/o addresses or generate ireq . cor1: pcmcia function 1 configuration register access: read/write address: 0x420 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d t e s e r sq e r l v e l] 5 [ x e d n i f n o c] 4 [ x e d n i f n o c] 3 [ x e d n i f n o c] 2 [ x e d n i f n o c] 1 [ x e d n i f n o c] 0 [ x e d n i f n o c sreset function 1 software reset. setting this bit to 1 drives the irq11/ rs 1 output signal from the AD1801 lo. irq11/ rs 1 is the function 1 reset signal when the AD1801 is configured in pcmcia mode. levlreq function 1 level mode ireq . level mode interrupts are defined when this bit is 1. pulse mode (edge trig- gered) interrupts are defined when this bit is 0. this bit is hardcoded to 1 (level mode interrupts). confindex[5:3] configuration index bits 5 through 3 are defined as vendor specific and are not used to control anything on the AD1801. these bits can be written and read for general scratchpad purposes. confindex[2] configuration index bit 2 enables ireq routing. when set to 1, ireq interrupts are enabled for function 1. when reset to 0, ireq interrupts are disabled for function 1. this bit is valid only when confindex[0] (func- tion enable) is set to 1 (enabled). confindex[1] configuration index bit 1 specifies the i/o addressing used. when set to 1, i/o addresses specified by the base and limit registers are passed to function 1. when reset to 0, all host i/o addresses are passed to function 1. this bit is valid only when confindex[0] (function enable) is set to 1 (enabled). confindex[0] configuration index bit 0 enables or disables function 1. when set to 1, function 1 is enabled. when reset to 0, function 1 is disabled and does not decode i/o addresses or generate ireq . cor2: pcmcia function 2 configuration register access: read/write address: 0x440 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d t e s e r sq e r l v e l] 5 [ x e d n i f n o c] 4 [ x e d n i f n o c] 3 [ x e d n i f n o c] 2 [ x e d n i f n o c] 1 [ x e d n i f n o c] 0 [ x e d n i f n o c sreset function 2 software reset. setting this bit to 1 drives the tfs/ rs 2 output signal from the AD1801 lo. sclk/ rs 2 is the function 2 reset signal when the AD1801 is configured in pcmcia mode. levlreq function 2 level mode ireq . level mode interrupts are defined when this bit is 1. pulse mode (edge trig- gered) interrupts are defined when this bit is 0. this bit is hardcoded to 1 (level mode interrupts). confindex[5:3] configuration index bits 5 through 3 are defined as vendor specific and are not used to control anything on the AD1801. these bits can be written and read for general scratchpad purposes. confindex[2] configuration index bit 2 enables ireq routing. when set to 1, ireq interrupts are enabled for function 2. when reset to 0, ireq interrupts are disabled for function 2. this bit is valid only when confindex[0] (func- tion enable) is set to 1 (enabled).
AD1801 C29C rev. 0 confindex[1] configuration index bit 1 specifies the i/o addressing used. when set to 1, i/o addresses specified by the base and limit registers are passed to function 2. when reset to 0, all host i/o addresses are passed to function 2. this bit is valid only when confindex[0] (function enable) is set to 1 (enabled). confindex[0] configuration index bit 0 enables or disables function 2. when set to 1, function 2 is enabled. when reset to 0, function 2 is disabled and does not decode i/o addresses or generate ireq . pcmcia card configuration and status registers csr0: pcmcia function 0 configuration and status register access: read/write address: 0x402 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d g n h cg h c g i s8 s i o i) 0 ( s e ro i d u an d r w pr t n ik c a r t n i chng status change detected. this bit indicates that one or more of the pin replacement register bits (cbvd1, cbvd2, crdy or cwprot) is set to one, normally causing the chg signal (pin 92) to be asserted; however, if the sigchg bit (see below) is 1, and the card is configured for an i/o interface, the chg pin is asserted when this bit is set. sigchg signal change enable/disable. this bit is set and reset by the host to enable and disable a status change signal from the status register. when this bit is set and the card is configured for the i/o interface, the chng bit controls pin 92 ( chg ). if no status change signal is desired, the bit should be set to zero and the chg signal will be held deasserted when the card is configured for i/o. iois8 i/o cycles occur only as 8-bit transfers. when the host can provide i/o cycles only using the sd7:sd0 data path, the pcmcia software will set this bit to a 1. the card is guaranteed that accesses to 16-bit registers will occur as two byte accesses rather than a single 16-bit access. this information is useful when 16-bit and 8-bit registers overlap. on the AD1801, this bit is hardcoded to 0 (16-bit transfers allowed). res reserved bits must be 0. audio audio enable. this bit enables audio information to be sent to the host bus adapter via the speaker pin spkr (pin 91) when configured for an i/o interface. pwrdn power-down. this bit is set to one to request that function 0 enter a power-down state. pcmcia software must not place function 0 into a power-down state while the functions ready pin in the lo (busy) state. intr interrupt request pending. this bit represents the internal state of the interrupt request. this value is available whether or not interrupts have been configured. how the intr bit is cleared is dependent up on how the intrack bit is configured. intrack = 0intr reflects the functions interrupt request status. if the interrupt is cleared within the function, intr is reset by the function. intrack = 1intr remains set even though the interrupt condition has been cleared (i.e., sticky). it is reset by system software to indicate it is ready to receive another interrupt (implemented to support interrupt sharing). intrack interrupt acknowledge. this bit determines the response of the intr bit. the functionality associated with the intrack bit permits two or more functions to share the pc cards ireq pin. intrack = 0when intrack is reset, intr functions as described above to support a single interrupt implementation. intrack = 1this causes the intr bit to remain set even though the interrupt service routine has already serviced the interrupt. normally, the interrupt service routine clears the interrupt pending bit in a function specific register, causing the intr also to be cleared; however, to support interrupt sharing, the intr bit is not cleared until pcmcia specific software is ready to handle the next interrupt request. when cleared by the pcmcia software, other inter- rupt requests that are pending can now be asserted over the pc cards ireq pin. csr1: pcmcia function 1 configuration and status register access: read/write address: 0x422 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d g n h cg h c g i s8 s i o i) 0 ( s e ro i d u an d r w pr t n ik c a r t n i chng status change detected. this bit indicates that one or more of the pin replacement register bits (cbvd1, cbvd2, crdy or cwprot) is set to one, normally causing the chg signal (pin 92) to be asserted. however, if the sigchg bit (see below) is 1, and the card is configured for an i/o interface, the chg pin is asserted when this bit is set. in the AD1801, chng is 0 for function 1.
AD1801 C30C rev. 0 sigchg signal change enable/disable. this bit is set and reset by the host to enable and disable a status change signal from the status register. when this bit is set, and the card is configured for the i/o interface, the chng bit controls pin 92 ( chg ). if no status change signal is desired, the bit should be set to zero and the chg signal will be held deasserted when the card is configured for i/o. in the AD1801, sigchg is 0 for function 1. iois8 i/o cycles occur only as 8-bit transfers. when the host can provide i/o cycles only using the sd7:sd0 data path, the pcmcia software will set this bit to a 1. the card is guaranteed that accesses to 16-bit registers will occur as two byte accesses rather than a single 16-bit access. this information is useful when 16-bit and 8-bit registers overlap. on the AD1801, this bit is hardcoded to 0 (16-bit transfers allowed). res reserved bits must be 0. audio audio enable. this bit enables audio information to be sent to the host bus adapter via the speaker pin spkr (pin 91) when configured for an i/o interface. in the AD1801, audio is 0 for function 1. pwrdn power-down. this bit is set to one to request that function 1 enter a power-down state. pcmcia software must not place function 1 into a power-down state while the functions ready pin is in the lo (busy) state. intr interrupt request pending. this bit represents the internal state of the interrupt request. this value is available whether or not interrupts have been configured. how the intr bit is cleared is dependent up on how the intrack bit is configured. intrack = 0intr reflects the functions interrupt request status. if the interrupt is cleared within the function, then intr is reset by the function. intrack = 1intr remains set even though the interrupt condition has been cleared (i.e., sticky). it is reset by system software to indicate it is ready to receive another interrupt (implemented to support interrupt sharing). intrack interrupt acknowledge. this bit determines the response of the intr bit. the functionality associated with the intrack bit permits two or more functions to share the pc cards ireq pin. intrack = 0when i ntrack is reset, intr functions as described above to support a single interrupt im plementation. intrack = 1this causes the intr bit to remain set even though the interrupt service routine has already serviced the interrupt. normally, the interrupt service routine clears the interrupt pending bit in a function specific regis- ter, causing the intr also to be cleared; however, to support interrupt sharing, the intr bit is not cleared until pc- mcia specific software is ready to handle the next interrupt request. when cleared by the pcmcia software, other interrupt requests that are pending can now be asserted over the pc cards ireq pin. csr2: pcmcia function 2 configuration and status register access: read/write address: 0x442 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d g n h cg h c g i s8 s i o i) 0 ( s e ro i d u an d r w pr t n ik c a r t n i chng status change detected. this bit indicates that one or more of the pin replacement register bits (cbvd1, cbvd2, crdy or cwprot) is set to one, normally causing the chg signal (pin 92) to be asserted. however, if the sigchg bit (see below) is 1 and the card is configured for an i/o interface, the chg pin is asserted when this bit is set. in the AD1801, chng is 0 for function 2. sigchg signal change enable/disable. this bit is set and reset by the host to enable and disable a status change signal from the status register. when this bit is set and the card is configured for the i/o interface, the chng bit controls pin 92 ( chg ). if no status change signal is desired, the bit should be set to zero and the chg signal will be held deasserted when the card is configured for i/o. in the AD1801, sigchg is 0 for function 2. iois8 i/o cycles occur only as 8-bit transfers. when the host can provide i/o cycles using only the sd7:sd0 data path, the pcmcia software will set this bit to a 1. the card is guaranteed that accesses to 16-bit registers will occur as two byte accesses rather than a single 16-bit access. this information is useful when 16-bit and 8-bit registers overlap. on the AD1801, this bit is hardcoded to 0 (16-bit transfers allowed). res reserved bits must be 0. audio audio enable. this bit enables audio information to be sent to the host bus adapter via the speaker pin spkr (pin 91) when configured for an i/o interface. in the AD1801, audio is 0 for function 2.
AD1801 C31C rev. 0 pwrdn power-down. this bit is set to one to request that function 2 enter a power-down state. pcmcia software must not place function 2 into a power-down state while the functions ready pin is in the lo (busy) state. intr interrupt request pending. this bit represents the internal state of the interrupt request. this value is available whether or not interrupts have been configured. how the intr bit is cleared is dependent upon how the intrack bit is configured. intrack = 0intr reflects the functions interrupt request status. if the interrupt is cleared within the function, intr is reset by the function. intrack = 1intr remains set even though the interrupt condition has been cleared (i.e., sticky). it is reset by system software to indicate it is ready to receive another interrupt (implemented to support interrupt sharing). in the AD1801, intr is 0 for function 2. intrack interrupt acknowledge. this bit determines the response of the intr bit. the functionality associated with the intrack bit permits two or more functions to share the pc cards ireq pin. intrack = 0when intrack is reset, intr functions as described above to support a single interrupt implementation. intrack = 1this causes the intr bit to remain set even though the interrupt service routine has already serviced the interrupt. normally the interrupt service routine clears the interrupt pending bit in a function specific register, causing the intr to also be cleared; however, to support interrupt sharing, the intr bit is not cleared until pcmcia specific software is ready to handle the next interrupt request. when cleared by the pcmcia software, other interrupt requests that are pending can now be asserted over the pc cards ireq pin. in the AD1801, intrack is ignored for function 2. pcmcia extended status register esr0: pcmcia function 0 extended status register access: read/write address: 0x408 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 3 t n e v e2 t n e v e1 t n e v en t t a q e r3 e l b a n e2 e l b a n e1 e l b a n ee l b a n e n t t a e r event3 reserved for future expansion/definitionmust be reset (0). event2 reserved for future expansion/definitionmust be reset (0). event1 reserved for future expansion/definitionmust be reset (0). req attn this bit is latched within one (1) ms of an event occurring on the pc card, such as the start of each cycle of the ring frequency to indicate the presence of ringing on the phone line in the case of a modem card. when this bit is set to a one (1), and the req attn enable bit is set to a one (1), the changed bit in the configuration and status register will also be set to a one (1), and if the sigchg bit in the configuration and status register has also been set by the host, the chg pin (pin 91) will be asserted. the host writing a one (1) to this bit will reset it to zero (0). writing a zero (0) to this bit will not have any effect. enable3 reserved for future expansion/definitionmust be reset (0). enable2 reserved for future expansion/definitionmust be reset (0). enable1 reserved for future expansion/definitionmust be reset (0). req attn enable setting this bit to a one (1) enables the setting of the changed bit in the configuration and status register wh en the req attn bit is set. when this bit is reset to a zero (0), this feature is disabled. the state of the req attn bit is not affected by the req attn enable bit. pcmcia i/o base registers iobl0: pcmcia function 0 i/o low base register address: 0x40a 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d ] 7 [ 0 l b o i] 6 [ 0 l b o i] 5 [ 0 l b o i] 4 [ 0 l b o i] 3 [ 0 l b o i] 2 [ 0 l b o i] 1 [ 0 l b o i] 0 [ 0 l b o i iobl0[7:0] low order byte of i/o base for function 0. iobl1: pcmcia function 1 i/o low base register address: 0x42a 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d ] 7 [ 1 l b o i] 6 [ 1 l b o i] 5 [ 1 l b o i] 4 [ 1 l b o i] 3 [ 1 l b o i] 2 [ 1 l b o i] 1 [ 1 l b o i] 0 [ 1 l b o i iobl1[7:0] low order byte of i/o base for function 1.
AD1801 C32C rev. 0 pwrdn power-down. this bit is set to one to request that function 2 enter a power-down state. pcmcia software must not place function 2 into a power-down state while the functions ready pin is in the lo (busy) state. intr interrupt request pending. this bit represents the internal state of the interrupt request. this value is available whether or not interrupts have been configured. how the intr bit is cleared is dependent upon how the intrack bit is configured. intrack = 0intr reflects the functions interrupt request status. if the interrupt is cleared within the function, intr is reset by the function. intrack = 1intr remains set even though the interrupt condition has been cleared (i.e., sticky). it is reset by system software to indicate it is ready to receive another interrupt (implemented to support interrupt sharing). in the AD1801, intr is 0 for function 2. intrack interrupt acknowledge. this bit determines the response of the intr bit. the functionality associated with the intrack bit permits two or more functions to share the pc cards ireq pin. intrack = 0when intrack is reset, intr functions as described above to support a single interrupt implementation. intrack = 1this causes the intr bit to remain set even though the interrupt service routine has already serviced the interrupt. normally the interrupt service routine clears the interrupt pending bit in a function specific register, causing the intr to also be cleared; however, to support interrupt sharing, the intr bit is not cleared until pcmcia specific software is ready to handle the next interrupt request. when cleared by the pcmcia software, other interrupt requests that are pending can now be asserted over the pc cards ireq pin. in the AD1801, intrack is ignored for function 2. pcmcia extended status register esr0: pcmcia function 0 extended status register access: read/write address: 0x408 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 3 t n e v e2 t n e v e1 t n e v en t t a q e r3 e l b a n e2 e l b a n e1 e l b a n ee l b a n e n t t a e r event3 reserved for future expansion/definitionmust be reset (0). event2 reserved for future expansion/definitionmust be reset (0). event1 reserved for future expansion/definitionmust be reset (0). req attn this bit is latched within one (1) ms of an event occurring on the pc card, such as the start of each cycle of the ring frequency to indicate the presence of ringing on the phone line in the case of a modem card. when this bit is set to a one (1), and the req attn enable bit is set to a one (1), the changed bit in the configuration and status register will also be set to a one (1), and if the sigchg bit in the configuration and status register has also been set by the host, the chg pin (pin 91) will be asserted. the host writing a one (1) to this bit will reset it to zero (0). writing a zero (0) to this bit will not have any effect. enable3 reserved for future expansion/definitionmust be reset (0). enable2 reserved for future expansion/definitionmust be reset (0). enable1 reserved for future expansion/definitionmust be reset (0). req attn enable setting this bit to a one (1) enables the setting of the changed bit in the configuration and status register wh en the req attn bit is set. when this bit is reset to a zero (0), this feature is disabled. the state of the req attn bit is not affected by the req attn enable bit. pcmcia i/o base registers iobl0: pcmcia function 0 i/o low base register address: 0x40a 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d ] 7 [ 0 l b o i] 6 [ 0 l b o i] 5 [ 0 l b o i] 4 [ 0 l b o i] 3 [ 0 l b o i] 2 [ 0 l b o i] 1 [ 0 l b o i] 0 [ 0 l b o i iobl0[7:0] low order byte of i/o base for function 0. iobl1: pcmcia function 1 i/o low base register address: 0x42a 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d ] 7 [ 1 l b o i] 6 [ 1 l b o i] 5 [ 1 l b o i] 4 [ 1 l b o i] 3 [ 1 l b o i] 2 [ 1 l b o i] 1 [ 1 l b o i] 0 [ 1 l b o i iobl1[7:0] low order byte of i/o base for function 1.
AD1801 C33C rev. 0 rngia host pc interrupt from ring pin acknowledge. in isa mode, ring pin initiated interrupts to the host pc are cleared by writes to this bit. each time a 1 is written to this bit, the rngi (host pc interrupt request from ring pin) bit in the pc i/o mapped register pcs is cleared to 0. writing a 0 to this bit has no effect on rngi. dspie host pc interrupt from dsp enable. used only in isa mode. this bit determines if a pending host interrupt request from the dsp, indicated by the dspi bit in the pcs register being set to 1, can cause a host interrupt. the state of this bit does not however effect the ability to set and clear the dspi bit itself. 0 = irq to host when dspi equals 1 disabled (default) 1 = irq to host when dspi equals 1 enabled rngie host pc interrupt from ring pin enable. used only in isa mode. this bit determines if a pending host interrupt from the ring pin, indicated by the rngi bit in the pcs register being set to 1, can cause a host interrupt. the state of this bit does not, however, effect the ability to set and clear the rngi bit itself. 0 = irq to host when rngi equals 1 disabled (default) 1 = irq to host when rngi equals 1 enabled int dsp interrupt. the dsp is sent an interrupt pulse via irq2 each time a 1 is written to this bit. note: irq2 must be configured in the dsp to be edge-sensitive. rst dsp reset. each time this bit is set to 1, the dsp is sent a reset pulse. setting this bit to 1 also causes: 1) the dsp reset source indicator bits (see drst[1:0] in the dsp i/o mapped register ip) to be set to 11; and 2) the codec channel e nable bits (see men, hen and msen in the dsp i/o mapped register cc) to be reset to 0. pd AD1801 power-down. writing a 1 to this bit initiates the process of powering down the AD1801. writing a 0 to this bit has no effect. a read of this bit will always return a 0. see the power consumption section of this docu- ment for important additional details. default state after reset: 0000 0000 0000 0000 (0x0000). pc status mnemonic: pcs access: read only address offset: 0x0 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d i p s di g n rs e rs e rs e rs e rs e rs e r 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d s e rs e rs e rs e rs e rs e rs e rs e r dspi2 host pc interrupt request from dsp. this bit is set to 1 whenever the dsp writes a 1 to the pcirq (host pc interrupt request) bit in the dc (dsp control) register. this bit is cleared each time the host pc writes a 1 to the dspia (host pc interrupt from dsp acknowledge) bit in the pcc (pc control) register. when set to 1, a host pc interrupt will be generated by driving the selected irq pin lo provided: 1) the AD1801 is in isa mode; 2) host pc interrupts from the dsp are enabled (see the dspie bit in the pcc register); and 3) an interrupt from the ring pin is not already active, i.e., the irq pin is not already driven lo. if a ring pin interrupt is already active, the dsp interrupt will be postponed until 500 to 600 ns after the ring pin interrupt is cleared, provided all conditions necessary to generate a dsp interrupt are still active. although this bit is not used in pcmcia mode to generate host interrupts, it may still be monitored to aid in distinguishing between dsp and ring pin interrupts provided it is cleared at the appropriate times. rngi host pc interrupt request from ring pin. this bit is set to 1 whenever the ring pin is driven from hi to lo. this bit is cleared each time the host pc writes a 1 to the rngia (host pc interrupt from ring pin acknowl- edge) bit in the pcc (pc control) register. when set to 1, a host pc interrupt will be generated by driving the selected irq pin lo provided: 1) the AD1801 is in isa mode; 2) host pc interrupts from the ring pin are enabled (see the rngie bit in the pcc register); and 3) an interrupt from the dsp is not already active, i.e., the irq pin is not already being driven lo. if a dsp interrupt is already active, the ring pin interrupt will be postponed until 500 to 600 ns after the dsp interrupt is cleared, providing all conditions necessary to generate a ring pin interrupt are still active. although this bit is not used in pcmcia mode to generate host interrupts, it may still be monitored to aid in distinguishing between dsp and ring pin interrupts, provided it is cleared at the appropriate times. default state after reset: 0000 0000 0000 0000 (0x0000).
AD1801 C34C rev. 0 internal dma control mnemonic: idmac access: write only address offset: 0x2 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s w re p y t3 1 a m2 1 a m1 1 a m0 1 a m9 a m8 a m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 a m6 a m5 a m4 a m3 a m2 a m1 a m0 a m note: after writing this register, the mdi register must not be read for at least 250 ns (assuming a 16.9344 mhz clock input on the xtali pin). performing a dummy read of the pcs register immediately after writing this register would be one way of satisfy ing this required delay. rws read or write select. specifies which dma access is enabled. 0 = read access via register mdi enabled (write access via mdo register ignored) 1 = write access via register mdo enabled (read access via mdi yield data) type memory type select. specifies the memory type accessed by reads of the mdi register or writes to the mdo regi ster. 0 = program memory accessed 1 = data memory accessed ma[13:0] memory address. specifies an initial memory address to be read via reads of the mdi register, or written via writes to the mdo register. after either a read or a write, this address is auto-incremented. default state after system reset: 0000 0000 0000 0000 (0x0000). memory data inputs mnemonic: mdi access: read only address offset: 0x4 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 i d m4 1 i d m3 1 i d m2 1 i d m1 1 i d m0 1 i d m9 i d m8 i d m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 i d m6 i d m5 i d m4 i d m3 i d m2 i d m1 i d m0 i d m mdi[15:0] memory data input. reading this register returns stale data if idma read access is not enabled. see the rws bit in register idmac. when reading program memory: the upper 16 bits of the 24-bit program memory word are read by a first read of this register. the lowest eight bits of the program memory word are read on bits 7:0 of this register by the next read of this register. during th e second read, bits 15:8 are always read as zeros. memory data output mnemonic: mdo access: write only address offset: 0x4 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 o d m4 1 o d m3 1 o d m2 1 o d m1 1 o d m0 1 o d m9 o d m8 o d m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 o d m6 o d m5 o d m4 o d m3 o d m2 o d m1 o d m0 o d m mdo[15:0] memory data output. writes to this register are ignored if idma write access is not enabled. see the rws bit in register idmac. when writing program memory: the upper 16 bits of the 24-bit program memory word are written by a first write to this register. the lowest eight bits of the program memory word are written via bits 7:0 of this register by the next write to this register. during the second write, bits 15:8 are ignored. test modes mnemonic: tm access: write only address offset: 0x6 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 m t4 1 m t3 1 m t2 1 m t1 1 m t0 1 m t9 m t8 m t 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 m t6 m t5 m t4 m t3 m t2 m t1 m t0 m t tm[15:0] tbd test mode control bits. default state after system reset: 0000 0000 0000 0000 (0x0000).
AD1801 C35C rev. 0 dsp i/o memory map the AD1801 uses the dsps ioms control and a 10-bit address a(9:0) to qualify dsp accesses to the internal cis ram, registers and i/o port pins addressed according to the table below. the host pc will not access the cis ram until it detects the deactiva tion of the ireq bus signal after a system reset. the dsp has control over the deactivation of this pin after a reset has occurred via the rdy bit in the dsp control register. under normal operations, the dsp will initialize the cis ram, then set the rdy bit; it wil l not access the cis memory again until after the next reset. an additional qualifying control, the dc register ovride bit, is us ed to determine whether the dsp can access the pnp function registers listed in the table or not. (the dsp must set this bit to a log ical 1 to temporarily take the pnp function off-line from the host pc in order to initialize or configure the pnp function itsel f. the dsp clears this bit to return the pnp function back on-line for host pc use.) note: i/o memory space must be set for at least one wait state for proper AD1801 functionality. table x. dsp i/o memory map dsp address resource accessed bits a[13:0] reads writes function 0x000C0x1ff reserved cis ram pcmcia or pnp attribute configuration 0x200 dc dc dsp control 0x201 reserved ipc i/o port control 0x202 ip op i/o port data 0x203 reserved ba base address 0x204 reserved is interrupt select 0x205 cc cc codec configuration 0x206 msr msr modem sample rate 0x207 hsr hsr handset sample rate 0x208 ml ml modem levels 0x209 hl hl handset levels 0x20a reserved msd monitor speaker data program memory organization program memory organization is controlled by the value of the pmovlay register. for the AD1801, valid settings of this register are 0 and 4. when set to 0, all 16k of internal program memory ram may be addressed. when set to 4, the upper 8k is swapped out and replaced with the 4080 word rom. after a dsp reset, pmovlay defaults to 4 and code execution commences at the first rom address, which is 0x2000. table xi. program memory organization pmovlay = 4 (default after dsp reset) address program memory 0x0000C0x1fff lower 8k of internal ram 0x2000C0x2fef 4080 words of internal rom 0x2ff0C0x2fff 16 words reserved for analog devices 0x3000C0x3fff reserved (invalid addresses) pmovlay = 0 address program memory 0x0000C0x1fff lower 8k of internal ram 0x2000C0x3fff upper 8k of internal ram cis ram access: write only address 0x000 to 0x1ff 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d d e r o n g id e r o n g id e r o n g id e r o n g id e r o n g id e r o n g id e r o n g id e r o n g i
AD1801 C36C rev. 0 data[7:0] only one byte of data may be written to the cis ram per cycle, and it must be msb justified on the 16-bit dsp data bus. each cis ram address points to a single byte. if in pnp mode: the pnp identifier must be written into the first nine bytes of the cis ram, i.e., addresses 0x000 to 0x008. immediately after the pnp identifier, the pnp resource data must be loaded. resource data may use any number of the remaining 503 cis ram bytes. the first pnp identifier byte must be written into the cis ram within 1 ms after system reset ( reset pin) is deasserted. the remaining eight pnp identifier bytes must be loaded at a rate of one every 2 ms or faster. resource data may be written into the cis ram at any rate. all bytes, whether pnp identifier or resource data, must be written into cis ram consecutively, and in a single pass. if in pcmcia mode: writes of tuples may be at any rate and in any order. once the cis ram is configured, the rdy bit in register dc must be set to 1 to indicate cis ram load completion. after setting the rdy bit to 1, further writes to cis ram must not occur. dsp control mnemonic: dc access: read/write address: 0x200 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d x i p s dx i g n rq r i c ps e rs a p y by d rw b d 1 p fw b d 2 p f 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d e d o m pt r o p s pn a h c p sa 1 0 o it i a w b sm r d pn r d pd p dspix alternate dsp access for pc i/o mapped register bits. reading this bit returns the state of the dspi bit in the pc i/o memory mapped register pcs. writing this bit is identical to writing the dspia bit in the pc i/o memory mapped register pcc. rngix alternate dsp access for pc i/o mapped register bits. reading this bit returns the state of the rngi bit in the pc i/o memory mapped register pcs. writing this bit is identical to writing the rngia bit in the pc i/o memory mapped register pcc. pcirq pc interrupt request. if in isa or pcmcia mode, writing a 1 to this bit sets the dspi (host pc interrupt request from dsp) bit in the pc mapped i/o register pcs. in isa mode, an interrupt to the host pc is asserted if dspi is set to 1, provided dsp interrupts to the host are enabled (see bit dspie in pc i/o mapped register pcc). in pcmcia mode, dspi itself does not cause a host interrupt, but can be monitored to distinguish be- tween dsp and ring pin interrupts to the host pc. when in pcmcia mode, writing a 1 to pcirq sets csr0 bit 0 to a 1, in addition to setting dspi. if csr0 bit 0 is set to 1, an interrupt to the host pc is as- serted, provided dsp interrupts to the host are enabled (see cor0 bit 2) and the function is enabled (see cor0). bypas pnp bypass. used in isa mode only and ignored in pcmcia mode. when this bit is set to 0, the pnp_ std pin determines whether the AD1801 is in pnp or non-pnp mode. when set to 1, the pnp_ std pin is ignored, and the AD1801 is always in non-pnp mode. when in non-pnp mode, the ba and irq registers must be written to select base address and irq. 0 = pnp_ std pin selects mode 1 = pnp_ std pin ignored, non-pnp mode forced rdy cis memory initialized indicator. used in pcmcia mode only and ignored in isa mode. this bit should be changed from its reset default of 0 to 1 by the dsp once the dsp has completely initialized the cis ram. when set to 1, the ireq pin, which serves as the pcmcia ready pin at startup, is released from its reset default of lo and driven hi. this indicates to the pcmcia host bus adapter that the AD1801 has completed self-initialization and is ready to be accessed. fp1dbw pcmcia function port 1 data bus width identifier. used in pcmcia mode only and ignored in isa mode. this bit must be written by the dsp before the AD1801 indicates it is ready to proceed with configuration at startup, i.e., before or coincident with the rdy bit in this register being written to a 1. it is used to define the behavior of the iocs16 pin when function port 1 is read. 0 = pcmcia function port 1 is 8 bits 1 = pcmcia function port 1 is 16 bits fp2dbw pcmcia function port 2 data bus width identifier. used in pcmcia mode only and ignored in isa mode. this bit must be written by the dsp before the AD1801 indicates it is ready to proceed with configuration at startup, i.e., before or coincident with the rdy bit in this register being written to a 1. it is used to define the behavior of the iocs16 pin when function port 2 is read. 0 = pcmcia function port 2 is 8 bits 1 = pcmcia function port 2 is 16 bits
AD1801 C37C rev. 0 pmode port mode select. selects which feature is supported by pins 53 to 56, either the secondary pcmcia function port or a dsp serial port. when the dsp serial port is selected, data i/o to either the modem or the handset codec channels is sacrificed since both serial ports are nominally used within the AD1801 for codec communication. see the psport and spchan bits for further details on which codec channels are lost. 0 = pcmcia function port 2 activated (default) 1 = dsp serial port activated (modem or handset dsp data i/o is sacrificed) psport port serial port select. when pmode is reset to 0, this bit is ignored. when pmode is set to 1, this bit selects which of the two dsp serial ports is connected to pins 53 to 56. note that this bit, together with the spchan bit, determine whether the modem or the handset codec channels are sacrificed when a dsp serial port is assigned to pins 53 to 56. 0 = dsp port 0 assigned to pins 53 to 56 when pmode = 1 (default) 1 = dsp port 1 assigned to pins 53 to 56 when pmode = 1 spchan dsp serial port channel assignment. this bit selects which codec channel uses which dsp serial port for data communication. 0 = modem adc and dac data sent on sport 0, handset adc and dac data sent on sport 1 (default) 1 = modem adc and dac data sent on sport 1, handset adc and dac data sent on sport 0 io0ia io0 pin interrupt acknowl edge. writing a 1 to this bit ack nowledges and deasserts the dsps irql1 level interrupt. this interrupt is asserted any time the logical input level on the io0 pin changes state, either from hi to lo or lo to hi. sbwait system bus wait. this bit is used by the dsp when servicing a power-down interrupt to support entering and exiting AD1801 power-down mode. once this bit is set to 1, any future pc read/write cycles to the AD1801 will be extended through the assertion of the iochrdy/ wait pin. when reset to 0, iochrdy/ wait will be deasserted (if asserted) to allow completion of an extended bus cycle. resetting this bit to 0 is also the mecha- nism of clearing a power-down interrupt initiated by the pc (see pd bit in the pc i/o mapped register pcc), so this bit should be reset to 0 before exiting a power-down interrupt service routine, even if it was not set to 1. see the power-down section of this document for important additional details. pdrm power-down request from pcmcia. this bit reflects the state of the pwrdn bit in the pcmcia register csr0. while set to 1, level interrupt irql0 is asserted to the dsp. this bit may be used by the dsp to deter- mine the source of the irql0 interrupt, as the pdrn bit below also asserts irql0. writing to this bit has no effect. see the power-down section of this document for important additional details. pdrn power-down request from pdn pin. this bit reflects the state of the pwd pin. while the pwd pin is held lo, level interrupt irql0 is asserted to the dsp. this bit may be used by the dsp to determine the source of the irql0 interrupt, as the pdrm bit above also asserts irql0. writing to this bit has no effect. see the power-down section of this document for important additional details. pd AD1801 power-down. writing a 1 to this bit initiates the process of powering down the AD1801. writing a 0 to this bit has no effect. when read as a 1, this bit indicates that there is no active nonextended system bus access to the AD1801. see the power-down section of this document for further clarification and important additional details. default state after reset: 0000 0000 0000 0000 (0x0000). i/o port control mnemonic: ipc access: read/write address 0x201 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s e rs e rs e rs e rs e re i k c se i n e se i d s 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 c p i6 c p i5 c p i4 c p i3 c p i2 c p i1 c p i0 c p i sdie serial memory port data direction. determines directionality of the sdata pin. 0 = sdata is an output pin with logic level set by sdo bit (see op register). 1 = sdata is an input pin (default). senie serial data enable control direction. determines directionality of the sen pin. 0 = sen is an output pin with logic level set by sen bit (see op register) (default). 1 = sen is an input pin. sckie serial data clock direction. determines directionality of the sck pin. 0 = sck is an output pin with logic level set by sck bit (see op register) (default). 1 = sck is an input pin. ipc[7:0] i/o port control. defines directionality of associated i/o port pins io7 through io0. 0 = output 1 = input (default) default state after system reset: 0000 0001 1111 1111 (0x01ff).
AD1801 C38C rev. 0 input port/status mnemonic: ip access: read only address 0x202 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 1 t s r d0 t s r dg n i rz d t s _ p n pz a s i _ m c pk c sn e si d s 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 p i6 p i5 p i4 p i3 p i2 p i1 p i0 p i drst[1:0] dsp reset indicator. these bits identify the source of the most recent dsp reset. 00 = last dsp reset was hard and from reset pin (power-up reset) 01 = last dsp reset was hard and from reset pin (isa reset) 10 = last dsp reset was soft and from pnp or pcmcia 11 = last dsp reset was soft and from rst bit in pc i/o memory mapped register pcc ring ring pin status. reflects the logic level on the ring pin. pnp_stdz isa mode configuration status. reflects the logic level on the pnp_ std pin. 0 = standard mode (pnp disabled: base address set by ba register, irq set by is register) 1 = pnp mode when the AD1801 is configured in pcmcia mode (i.e., when the pcm_ isa pin is hi), then the pnp_ std pin can be used as a general purpose input. the pnp_stdz register bit can be used to monitor the state of this general purpose input under those conditions. pcm_isaz AD1801 operating mode status. reflects the logic level on the pcm_ isa pin. 0 = isa mode 1 = pcmcia mode sck serial data clock status. reflects the logic level on the sck pin. sen serial data enable control status. reflects the logic level on the sen pin. sdi serial data in pin status. reflects the logic level on the sdata pin. ip[7:0] i/o port input state. reflects the logic levels on associated i/o port pins io7 through io0. i/o port pins not connected externally are evaluated as logic 1 due to internal pull-up resistors. will drive a weak hi level externally. default state after system reset: 0000 x0xx xxxx xxxx (0x0xxx). output port mnemonic: op access: write only address 0x202 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s e rs e rs e rs e rs e rk c sn e so d s 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 p o6 p o5 p o4 p o3 p o2 p o1 p o0 p o sck serial memory port clock output. the state of this bit is reflected on the sck pin. sen serial memory port chip enable output. the state of this bit is reflected on the sen pin. sdo serial memory port data output. the state of this bit is reflected on the sdata pin provided bit sdie (register ipc) is reset to 0. op[7:0] i/o port output state. defines the logic levels to be driven out on i/o port pins io7 through io0 provided the associated i/o port control bit in the ipc register is reset to 0. default state after system reset: 0000 0000 1111 1111 (0x00ff). default base address mnemonic: ba access: write only address 0x203 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 2 1 a b1 1 a b0 1 a b9 a b8 a b7 a b6 a b5 a b 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 4 a b3 a b2 a b1 a b0 a bs e rs e rs e r
AD1801 C39C rev. 0 ba[12:0] default base address. these bits are used to qualify host pc i/o access to the AD1801 if either in non-pnp isa mode (pcm_ isa pin tied lo and pnp_ std pin tied lo), or if the bypas bit in the dsp control (dc) register is set to 1. note: this register always qualifies host pc i/o access, but the dsp must initialize it when the AD1801 is configured in non-pnp isa mode, since pnp/pcmcia hardware/software does not. note that independent of mode, the dsp can always write the base address register, but under the obvious risk of interfering with pnp isa or pcmcia transactions. default state after system reset: 0000 0000 0000 0000 (0x0000). default interrupt select mnemonic: is access: write only address 0x204 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 2 p t n i1 p t n ie d o m ss e rs e rs e rs e rs e r 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d s e rs e rs e rs e r3 s i2 s i1 s i0 s i intp2 interrupt edge polarity for pcmcia function 2. this bit is ignored unless in pcmcia mode. it defines the edge necessary on the int2 pin to cause a function 2 interrupt. 0 = falling edge interrupt (default). 1 = rising edge interrupt. intp1 interrupt edge polarity for pcmcia function 1. this bit is ignored unless in pcmcia mode. it defines the edge necessary on the int1 pin to cause a function 1 interrupt. 0 = falling edge interrupt (default). 1 = rising edge interrupt. smode strobe mode. this bit selects the functionality of pins 82 and 94 when the AD1801 is in pcmcia mode. 0 = pins 82 and 94 function as vctl2 and vctl1, respectively (default) 1 = pins 82 and 94 function as extwr and extrd , respectively. is[3:0] default interrupt request. these bits are ignored unless in isa mode (pcm_ isa pin tied lo). when in isa mode, these bits select the AD1801 irq if either in non-pnp mode (pnp_ std pin tied lo), or if the dc register bypas bit is set to 1. valid settings for is[3:0] are: 3, 4, 5, 7, 9, 10, 11, 12 and 15. other settings are ignored and result in no irq selection. note: this register always selects the AD1801 irq when in isa mode, but the dsp must initialize it when the AD1801 is configured in non-pnp isa mode, since pnp/pcmcia hardware/software does not. note that independent of mode, the dsp can always write to the interrupt select register, but under the obvious risk of interfering with pnp isa transactions. default state after system reset: 0000 0000 0000 0000 (0x0000). codec configuration mnemonic: cc access: read/write address 0x205 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s e rs f d mt c l m1 m s m0 m s mr s s m0 d s s m2 r d s s m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 1 r d s s m0 r d s s mn e a s mn e mn e hn e s mn e b sn e c mdfs modem digital filter select. this bit is used to select which of two digital filters is applied to the modem adc and dac channels. the first choice has been optimized for filter performance, while the second choice has been optimized for a reduced linear group delay. passband stopband mdfs ripple 1 edge C3 db point ripple 2 edge linear group delay 0 C017 db 0.445 msr 0.490 msr AD1801, the corner frequency of this analog filter is too high to have a substantial effect when low sa mple rates are used. consult the filter plots at the end of this document for further details.
AD1801 C40C rev. 0 frequency range roll-off 0 khz to 4 khz <0.0016 db 4 khz to 9 khz <0.01 db 9 khz to 16 khz <0.05 db 16 khz to 20 khz <0.10 mlct modem dac level change timing. this bit controls when changes to the modem dac level (see mdam and mdal[4:0] bits in the ml register) take effect. when reset to 0, changes take effect immediately. when set to 1, changes are delayed until either the output level crosses zero (midscale), or until a 10 ms to 12 ms timeout period is reached. delaying level changes until zero crossings reduces instantaneous output voltage changes, that reduces audible clicks. 0 = level changes applied immediately (default) 1 = level changes applied on signal zero (midscale) crossing or after 10 msC12 ms timeout msm[1:0] modem sample rate modifier. these bits are used to select the lsb weighting of the msr[15:0] (modem sample rate) bits in the msr register. 00 = msr[15:0] lsb weight is 1 hertz (default) 01 = msr[15:0] lsb weight is 8/7 hertz 10 = msr[15:0] lsb weight is 10/7 hertz 11 = reserved mssr monitor speaker sample rate select. 0 = monitor speaker sample rate locked to modem sample rate (see msr register) 1 = monitor speaker sample rate locked to handset sample rate (see hsr register) mssdo monitor speaker sigma-delta order and bitstream density select. available in pcmcia mode or in isa mode. setting this bit to a 1 will double the nominal output volume from a speaker connected to the spkr pin or the mspkr pin, but will also significantly increase output noise. the state of the mssdo bit should only be changed when the monitor speaker is powered down (i.e., msen = 0). 0 = third order modulator with 75%/25% bitstream positive/negative full-scale mapping 1 = first order modulator with 100%/0% bitstream positive/negative full-scale mapping mssdr[2:0] monitor speaker sigma-delta bitstream rate select. used in pcmcia mode only and ignored in isa mode. these bits may be used to decrease the nominal output bitstream rate sent to the spkr pin. a decreased bitstream rate will allow more time for a piezoelectric speaker to properly discharge before being redriven, but will also de- crease the oversampling rate, resulting in more output noise. the state of the mssdr[2:0] bits should only be changed when the monitor speaker is powered down (i.e., msen = 0). 0xx = 1411.2 khz bitstream rate (default) 100 = 705.6 khz bitstream rate 101 = 352.8 khz bitstream rate 110 = 176.4 khz bitstream rate 111 = 88.2 khz bitstream rate msaen monitor speaker analog output enable. used in pcmcia mode only and ignored in isa mode. 0 = analog monitor speaker output (pin mspkr) always powered down 1 = analog monitor speaker output (pin mspkr) powered up when msen is set to 1 men modem enable. up to 100 m s are required to enable (power-up) the modem codec channels once the codec is enabled (see bit cen). approximately 30 m s are required to power down these channels if mlct (modem dac level change timing) is reset to 0. both power-up and power-down are internally sequenced to minimize instantaneous output voltage changes; however, the power-down sequence for this channel may be quieter if mlct is set to 1. 0 = modem adc and dac power-down (default) 1 = modem adc and dac enabled provided cen (codec enable bit) is set to 1 hen handset enable. up to 100 m s are required to enable (power-up) the handset codec channels once the codec is enabled (see bit cen). approximately 30 m s are required to power down these channels. both power-up and power- down are internally sequenced to minimize instantaneous output voltage changes (i.e., pops and clicks). 0 = handset adc and dac powered-down (default) 1 = handset adc and dac enabled provided cen (codec enable bit) is set to 1 msen monitor speaker enable. up to 100 m s are required to enable (power up) the monitor speaker dac channel once the dac is enabled (see bit cen). approximately 30 m s are required to power down this channel. both power-up and power-down are internally sequenced to minimize instantaneous output voltage changes (i.e., pops and clicks). 0 = monitor speaker dac powered down (default) 1 = monitor speaker dac enabled provided cen (codec enable bit) = 1
AD1801 C41C rev. 0 sben codec standby enable. if either this bit or the cen (codec enable) bit is set to 1, the process of powering up the AD1801s codec voltage reference is initiated. if both this bit and the cen bit are reset to 0, the process of power- ing down the AD1801s codec voltage reference is initiated. approximately 700 ms are required to power up the codec voltage reference while only 30 ns are required to power it down. this bit may be used to keep the codec volt- age reference powered up when the rest of the codec is powered down, which results in a much quicker power-up sequence. see the cen bit for further details. 0 = codec powered down (provided cen = 0) (default) 1 = codec in standby (provided cen = 0) cen codec enable. when a 1 is written to this bit, the process of powering up the AD1801 codecs is initiated. when a 0 is written to this bit, the process of powering down the AD1801 codecs is initiated. w hen read as a 0, the codecs are either powered down or in the process of powering up. when read as a 1, the codecs are either powered up or in the process of powering down. therefore, completion of the process of powering up or down can be detected by writ- ing the appropriate value to this bit and reading this bit until the written value is echoed. power-up normally requires no more than 700 ms, but up to 840 ms will be required the first time the codecs are powered up after an AD1801 reset, since this is when the codecs perform an autocalibration. note that if the codecs are first put in standby using the sben bit (and given 700 ms time to complete the transition into standby), only 30 ns will be required after set- ting the cen bit to 1 to complete the power-up process. powering down the codecs never requires more than 150 ns. see table xii for a complete summary. default state after system reset: 0000 0000 0000 0000 (0x0000). modem sample rate mnemonic: msr access: read/write address: 0x206 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 r s m4 1 r s m3 1 r s m2 1 r s m1 1 r s m0 1 r s m9 r s m8 r s m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 r s m6 r s m5 r s m4 r s m3 r s m2 r s m1 r s m0 r s m msr[15:0] modem sample rate. together with msm[15:0] (modem sample rate modifier) in the cc register, these bits define the conversion rate for the modem adc and dac channels. if the mssr bit (monitor speaker sample rate select) in register cc is reset to 0 (default), these bits also define the conversion rate for the monitor speaker dac. with a 16.9344 mhz clock input on the xtali pin, one lsb represents: exactly 1 hertz when msm[1:0] = 00; exactly 8/7 hertz when msm[1:0] = 01; and exactly 10/7 hertz when msm[1:0] = 10. permitted settings of msr[15:0] range from: 5400 to 48000 when msm[1:0] = 00; 4725 to 42000 when msm[1:0] = 01; and 3780 to 33600 when msm[1:0] = 10. resultant sample rate, regardless of msm[1:0] setting, always ranges from 5400 hz to 48000 hz. default state after system reset: 0001 1100 0010 0000 (0x1c20) which is 7200 hz with msm[1:0] = 00. handset sample rate mnemonic: hsr access: read/write address: 0x207 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 r s h4 1 r s h3 1 r s h2 1 r s h1 1 r s h0 1 r s h9 r s h8 r s h 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 r s h6 r s h5 r s h4 r s h3 r s h2 r s h1 r s h0 r s h hsr[15:0] handset sample rate. defines the conversion rate for the handset adc and dac channels. if the mssr (monitor speaker sample rate select) bit in register cc is set to 1, these bits also define the conversion rate for the monitor speaker dac. one lsb represents exactly 1 hertz, assuming a 16.9344 mhz clock input on the xtali pin. usable range is 5400 hz (0x1518) to 48000 hz (0xbb80). default state after system reset: 0001 1111 0100 0000 (0x1f40) which is 8 khz. modem levels mnemonic: ml access: read/write address: 0x208 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s e rs e rs e rs e rs e rs e r1 l d a m0 l d a m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d m a d m4 l a d m3 l a d m2 l a d m1 l a d m0 l a d m1 l a d s0 l a d s
AD1801 C42C rev. 0 madl[1:0] modem adc gain level select. least significant bit represents +6.0 db. 00 = 0.0 db gain (default) 01 = +6.0 db gain 10 = +12.0 db gain 11 = reserved mdam modem dac mute. 0 = enabled 1 = muted (default) mdal[4:0] modem dac attenuation level select. least significant bit represents C1.0 db. 00000 = 0 db attenuation (default) 11111 = C31 db attenuation sdal[1:0] monitor speaker attenuation level. 00 = 0.0 db attenuation 01 = C6.0 db attenuation 10 = C12.0 db attenuation 11 = muted (default) default state after system reset: 0000 0000 1000 0011 (0x0083). handset levels mnemonic: hl access: read/write address: 0x209 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d s d a he g m hs e rs e r3 l d a h2 l d a h1 l d a h0 l d a h 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d m s a d hm l a d hs e r4 l a d h3 l a d h2 l a d h1 l a d h0 l a d h hads handset adc input select. 0 = mic (default) 1 = line hmge handset mic gain enable. 0 = 0 db gain (default) 1 = +20 db gain hadl[3:0] handset adc gain level select. least significant bit represents +1.5 db. 0000 = 0.0 db gain (default) 1111 = +22.5 db gain hdasm handset dac speaker mute. 0 = enabled 1 = muted (default) hdalm handset dac line mute. 0 = enabled 1 = muted (default). midscale voltage output on hspkrp and hspkrn hdal[4:0] handset dac attenuation level select. least significant bit represents C1.5 db. 00000 = +12.0 db gain 01000 = 0.0 db attenuation (default) 11111 = C34.5 db attenuation default state after system reset: 0000 0000 1100 1000 (0x00c8). modem speaker data mnemonic: msd access: write address: 0x20a 5 1 a t a d4 1 a t a d3 1 a t a d2 1 a t a d1 1 a t a d0 1 a t a d9 a t a d8 a t a d 5 1 d s m4 1 d s m3 1 d s m2 1 d s m1 1 d s m0 1 d s m9 d s m8 d s m 7 a t a d6 a t a d5 a t a d4 a t a d3 a t a d2 a t a d1 a t a d0 a t a d 7 d s m6 d s m5 d s m4 d s m3 d s m2 d s m1 d s m0 d s m msd[15:0] monitor speaker data. writes to this register fill a 16 deep fifo. if this fifo underruns, the last sample will be repeated to the monitor speaker dac for up to 16 consecutive underruns; thereafter, midscale sample data is used for all additional underruns. this avoids clicks due to momentary fifo underruns (easing playback startup) and avoids sustained dc output levels. data written to this fifo that would cause fifo overrun is ignored. no status bits are needed for this fifo since it is locked to either the modem or handset sample rate (see the mssr bit in register cc).
AD1801 C43C rev. 0 power consumption the AD1801 power consumption is dependent on many factors, including codec resources used, adsp-2181 core resources used and instruction mix. table xii provides some estimates of the maximum current consumption of the AD1801 as a function of device resources used. table xii. AD1801 current consumption estimates power system bus estimated states dsp codec interface max current 1mhs* active up: mod & hnd responsive 252 ma & spk enabled 1mh* active up: mod & hnd responsive 157 ma enabled 1s* active up: spk enabled responsive 220 ma 1h* active up: hnd enabled responsive 142 ma 1m* active up: mod enabled responsive 140 ma 1 active up: all channels responsive 125 ma disabled 2c active standby responsive 94 ma 2 active down responsive 92 ma r nop down nonresponsive 40 ma 3c idle standby responsive 19 ma 3 idle down responsive 17 ma 4c standby standby slow ? 5 ma responsive 4 standby down slow ? 3 ma responsive 5c down standby nonresponsive 2.5 ma 5 down down nonresponsive 0.5 ma *when in power state 1, any combination of the modem (mod), handset (hnd), and speaker (spk) channels may be enabled through the use of independent channel enable bits (see the dsp i/o mapped cc register). only the combina- tions thought most likely to be used have been listed. * current numbers assume: 1. 50% of instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are 1. type 2 and type 6, and 20% are idle. 2. device is operating with no isa/pcmcia pin loads. warning: for proper operation of the AD1801, dsp code must never: 1. use the idle(n) instruction (critical internal clocks will be slowed). 2. write the pdforce (power-down interrupt force) bit in the sport1 autobuffer control register to 1 (this would power down the AD1801 with no means of powering back up other than a pin reset). power-down states power state r dsp: running nop codec: powered down interface: nonresponsive crystal: enabled the AD1801 is forced into this power state any time one or both of the reset pins (reset and reset ) is asserted. the AD1801 will remain in this power state until both of the reset pins are deasserted. immediately after both reset pins are deasserted, the AD1801 will enter power state 2 and commence instruction execution at location 0x2000 rom. when power is first applied, the AD1801 must be kept in this power state (by the continuous assertion of at least one of the reset pins) until the clock input on the xtali pin stabilizes, plus another 1000 xtali cycles to allow the AD1801s phase locked loop to lock. with a crystal connected between the xtali and xtalo pins, the time required for the clock input to stabilize is dependent upon the type of crystal used and the capacitance of the external crystal circuit; typically 2000 xtali cycles is adequate. if the AD1801 was in power state 5 prior to the assertion of a pin reset, the procedure listed above for initial power-up must be followed since the clocks were stopped while in power state 5. if the AD1801 was in power state 1, 2, 3 or 4 prior to the asser- tion of a reset pin, the AD1801 must be kept in this power state (by the continuous assertion of at least one of the reset pins) for at least five xtali cycles. note that asserting a reset while in power state 1 is not recommended due to the noisy abrupt shutdown of the codec. power state 2 dsp: active codec: powered down or in standby interface: responsive crystal: enabled if the codec is in standby (see the sben bit in dsp i/o mapped register cc), its voltage reference circuitry is not powered down which results in greater power consumption; however, the time required to transition from power state 2 to power state 1 is decreased from approximately 500 ms to approximately 15 ms. if the cen (codec enable) bit is set to 1 (see dsp i/o mapped register cc), the process of entering power state 1 will be initiated. the dsp may poll the codec (by reading the cen bit and waiting for an echo of 1) to determine when power state 1 is actually entered. power state 3 will be entered if an idle instruction is executed by the dsp, provided the dsp is not currently servicing a power-down interrupt. note that the idle(n) dsp instruction must not be used since the internal clock slow down caused by this instruction will interfere with the AD1801 bus interface logic. power state 1 (any form) dsp: active codec: powered up. any combination of modem, handset and speaker codec channels enabled. interface: responsive crystal: enabled although the codec is powered up in this power state, the amount of power actually consumed is still dependent on the number of codec channels actually enabled. the modem (adc and dac), handset (adc and dac) and speaker (dac) chan- nels can be independently enabled and disabled using the men, hen and msen bits in dsp i/o mapped register cc. before enabling either the modem of handset codec channels, the dsp serial port used to communicate with the codec chan- nels must first be properly configured in the dsp. if serial port 0 is used, the sport 0 control register at 0x3ff6 must be set to 0x3c0f. if serial port 1 is used, the sport 1 control register at 0x3ff2 must be set to 0x3c0f. also, the used serial ports must be enabled by setting the appropriate bits in the
AD1801 C44C rev. 0 2. beginning at 0x002c, any number of housekeeping instruc- tions can be executed prior to the dsp entering actual power- down. these instructions must ensure that the codec is powered down before continuing with this procedure. see the cen (codec enable) bit located in the dsp i/o mapped register cc (codec configuration) for detailed information on how to power-down the codec and check its power-up/ -down status. these instructions must also program the sport1 autobuffer/power-down control r egister memory mapped at location 0x3fef to 0x0xxx unless these settings are made in advance. this sets: xtaldis = 0, which causes the crystal oscillator to stay enabled during dsp power- down. xtaldelay = 0, which causes the dsp startup delay to be less than 100 cycles. pdforce = 0, which should never be set to 1 in the AD1801. pucr = 0, which avoids a dsp power-up reset so instruction execution continues in the power-down handler after power-up. 3. the dsp must write a 1 to the sbwait (system bus wait) bit in dsp i/o mapped register dc. any bus transac- tions to the AD1801 started after this point will be ex- tended (through the assertion of the iochrdy/ wait pin) until the dsp wakes up again after being powered down by the steps below. any currently active bus access to the AD1801 will be completed without bus cycle extension to insure that the AD1801 doesnt assert iochrdy/ wait too close to the end of a bus access. 4. the dsp must poll the pd bit in the dsp i/o mapped dc register until it is read as a 1. in most systems, this will require no more than 1 m s. when read as a 1, this indicates that there is either no active system bus access to the AD1801, or that a bus access to the AD1801 has been stalled through the assertion of the iochrdy/ wait pin. once read as a 1, it is safe to power down the dsp and stop the AD1801 internal clocks. 5. the dsp powers itself down with the execution of an idle instruction. this completes the transition into power state 4. while the AD1801 is now mostly powered down, it contin- ues decoding bus traffic waiting for any AD1801 access, read or write, which will initiate AD1801 wakeup. note that ac- cesses to pcmcia external devices will occur without wak- ing up the AD1801. the process of entering power state 4 may be aborted up until step 4 where sbwait is set to 1. once set to 1, steps 4 and 5 must also be executed for proper future AD1801 operation. if sbwait was not set to 1, power state 4 can be aborted by first resetting sbwait to a 0, that signals an early exit to the AD1801, and then executing an rti ins truction which will exit the power-down handler. system control register at 0x3fff. finally, note that the pmode, psport and spchan bits in the dsp i/o mapped register dc, which specify dsp serial port usage, must also be defined before enabling related codec channels. if the cen (codec enable) bit is reset to 0 (see dsp i/o mapped register cc), the process of entering power state 2 will be initiated. the dsp may poll the codec (by reading the cen bit and waiting for an echo of 0) to determine when power state 2 is actually entered. power state 3 dsp: idle codec: powered down or in standby interface: responsive crystal: enabled power state 3 will be entered if an idle instruction is executed by the dsp, provided the dsp is not currently servicing a power-down interrupt. note that the idle(n) dsp instruction must not be used since the internal clock slow down caused by this instruction will interfere with the AD1801 bus interface logic. in this power state, the dsp is idle and the codec is powered down. when an unmasked interrupt occurs, the AD1801 will return to power state 2 immediately and service the interrupt. power state 4 dsp: powered down codec: powered down or in standby interface: slow responsive crystal: enabled entering and exiting this power state requires dsp code sup- port. this code is outlined below. while in this power state, the AD1801 will not be immediately responsive to system bus ac- cesses, but will extend bus cycles through the assertion of the iochrdy/ wait pin until able to respond. any system bus access to the AD1801, read or write, will wake the AD1801 from this power state and return it to power state 2 where the AD1801 can respond to bus cycles. the system bus will be stalled for no more than 7 m s, which is acceptable for both isa and pc mcia buses. the isa bus specifies a maximum stall of 15.6 m s, and the pcmcia bus specifies a maximum stall of 12 m s. entering power state 4: 1. the transition to power state 4 is initiated by the assertion of a nonmaskable power-down interrupt. the source of this power-down interrupt may be: 1) the pc writing to the pd bit in the pc i/o memory mapped register pcc; 2) the dsp writing the pd bit in dsp i/o memory mapped register dc. this interrupt will cause the dsp to vector to address 0x002c. the transition to this power state may be indirectly initiated by asserting the pwd (power-down pin) or the pcmcia power-down bit (bit pwrdn of register csr0). either of these actions will cause an irql0 interrupt to the dsp, causing it to vector to address 0x000c. in this inter- rupt handler, the dsp may in turn write the pd bit. note that the dsp has access to two flag bits (pdrn and pdrm in dsp i/o mapped register dc) that indicate the source of an irql0 interrupt.
AD1801 C45C rev. 0 exiting power state 4: 6. there are two conditions under which the dsp will be pow- ered up, and power state 4 exited. the first is the host pc initiating a read or write access to the AD1801. the second is a logic transition (either lo to hi or hi to lo) on any of the following input signals: ring, int1, and int2. 7. when the host initiates the read or write access, the AD1801 asserts the iochrdy/ wait pin to extend the bus cycle until it can respond, and begins the process of powering up the dsp. when the wake is caused by a transition on ring, int1, or int2, the iochrdy/ wait signal is not asserted. powering up the dsp requires about 6 m s. 8. when the dsp wakes up, it continues executing code where it left off in the power-down handler. the first instruction should reset the sbwait bit to 0 to allow the completion of the extended bus cycle. 9. any number of housekeeping instructions can now be ex- ecuted before the power-down interrupt handler is exited by an rti instruction. power state 4 may also be exited with the assertion of a pin reset, reset or reset . power state 5 dsp: powered down codec: powered down or in standby interface: nonresponsive crystal: disabled warning: when in this power state, bus accesses to the AD1801 are not possible. this power state must not be used if isa pnp or pcmcia configuration register access must be maintained. entering and exiting this power state requires dsp code support. this code is outlined below. while in this power state, the AD1801 will not be responsive to system bus ac- cesses. any system bus access to the AD1801, read or write, will, however, wake the AD1801 from this power state into power state 2. on the order of 280 m s plus a crystal settle time will be necessary to wake the AD1801. unlike waking from power state 4, bus cycles will not be extended when waking from this power state. entering power state 5: 1. the transition to power state 5 is initiated by the assertion of a nonmaskable power-down interrupt. the source of this power-down interrupt may be: 1) the pc writing to the pd bit in the pc i/o memory mapped register pcc; 2) the dsp writing the pd bit in dsp i/o memory mapped register dc. this interrupt will cause the dsp to vector to address 0x002c. the transition to this power state may be indirectly initiated by asserting the pwd (power-down pin) or the pcmcia power-down bit (bit pwrdn of register csr0). either of these actions will cause an irql0 interrupt to the dsp, causing it to vector to address 0x000c. in this inter- rupt handler, the dsp may in turn write the pd bit. note that the dsp has access to two flag bits (pdrn and pdrm in dsp i/o mapped register dc), which indicate the source of an irql0 interrupt. 2. beginning at 0x002c, any number of housekeeping instruc- tions can be executed prior to the dsp entering actual power- down. these instructions must insure that the codec is powered down before continuing with this procedure. see the cen (codec enable) bit located in the dsp i/o mapped register cc (codec configuration) for detailed information on how to power down the codec and check its power up/ down status. these instructions must also program the sport1 autobuffer/power-down control register memory mapped at location 0x3fef to 0x0xxx unless these settings are made in advance. this sets: xtaldis = 1, which causes the crystal oscillator to power down during dsp power-down. xtaldelay = 1, which causes the dsp startup delay to be 4096 clock cycles. pdforce = 0, which should never be set to 1 in AD1801. pucr = 0, which avoids a dsp power up reset so instruction execution continues in the power-down handler after power-up. 3. the dsp powers itself down with the execution of an idle instruction. this completes the transition into power state 5. while the AD1801 is now mostly powered down, it contin- ues decoding bus traffic waiting for any AD1801 access, read or write, that will initiate AD1801 wakeup. note that ac- cesses to pcmcia external devices will occur without wak- ing up the AD1801. the process of entering power state 5 may be aborted up until step 3 where the idle instruction is executed. power state 5 can be aborted by first resetting sbwait to a 0, which signals an early exit to the AD1801, and then execut- ing an rti instruction which will exit the power-down han dler. exiting power state 5: 4. there are two conditions under which the dsp will be pow- ered up, and power state 5 exited. the first is the host pc initiating a dummy read access to the AD1801. this bus access to the AD1801, and all others until the AD1801 is awake, is lost. the second is a logic state transition (either lo to hi or hi to lo) on any of the following input signals: ring, int1, and int2. 5. when the dsp wakes up, it continues executing code where it left off in the power-down handler. the first instruction should reset the sbwait bit to 0 to clear the power-down logic. 6. any number of housekeeping instructions can now be ex- ecuted before the power-down interrupt handler is exited by an rti instruction. it may be desirable to send an interrupt to the host pc to signal AD1801 wakeup. power state 5 may also be exited with the assertion of a pin reset, reset or reset .
AD1801 C46C rev. 0 start-up sequence the following paragraphs describe a typical, generic start-up sequence for the purpose of helping hardware, systems and software driver engineers understand some of the considerations involved in bringing up a system that includes the AD1801. note that it does not exhaustively outline all of the flexible configurations and features available in the AD1801. 1. system power supplies stabilize. 2. assert the reset and/or reset signals. 3. deassert the reset and/or reset signals. 4. power up the codecs. write 1 to the cen (codec enable) bit in the codec configuration register. this will initiate the process of powering up the AD1801 codecs (daa codec, handset codec and monitor speaker dac). poll this bit until the readback value is 1, which indicates that the codec power-up process is complete. the time required to power up the codec from the powered down state (not from cold start) depends on the state of the sben (standby enable) bit in the codec configuration register. codec power-up will take either 500 ms (sben = 0) or 15 ms (sben = 1). when sben is set to 1, the analog voltage reference is not powered down, so power-up is faster at the expense of higher power consumption in the powered down state. 5. power up the individual codec channels. write 1 to the men (modem enable) bit in the codec configuration register to power up the modem (daa) codec channel (adc and dac). power-up of the modem channel takes approximately 10 m s. write 1 to the hen (handset enable) bit in the codec configuration register to power-up the handset codec chan- nel (adc and dac). power up of the handset codec chan- nel takes approximately 10 m s. write 1 to the msen (monitor speaker enable) bit in the codec configuration register to power up the monitor speaker dac. power-up of the monitor speaker dac takes approximately 10 m s. boot-up sequence the AD1801 boot process is a combination of software and hardware operations. because much of the boot process is driven by software, it can be performed in a number of ways. the following steps provide a rough guideline. 1. once the power supplies have stabilized, the reset inter- rupt vectors the dsp program counter to dsp program memory address 0x2000, which is the first rom address when pmovlay = 4, and is the default after dsp reset. it then starts to execute the instructions which the oem has programmed into on-chip rom. these instructions would typically include dsp i/o writes to configure dsp resources (such as the sports) and the idma registers (such as the dags). table xiii. power state transitions time required indicator to dsp of initial state final state transition trigger (bits in cc register) for transition transition completion 2 1[m, h, s] cen set to 1, [men, hen, msen] set to 1 < 700 ms* cen read back as 1 1[m, h, s] 2 cen reset to 0, sben set to 1 < 100 m s* cen read back as 0 2c 1[m, h, s] cen set to 1, [men, hen, msen] set to 1 < 100 m s* cen read back as 1 1[m, h, s] 2c cen reset to 0, sben reset to 0 < 100 m s* cen read back as 0 1 1s msen set to 1 < 100 m s none 1s 1 msen reset to 0 < 100 m s none 1 1h hen set to 1 < 100 m s dsp sport activity 1h 1 hen reset to 0 < 100 m s sport activity stops 1 1m men set to 1 < 100 m s dsp sport activity 1m 1 men reset to 0 < 100 m s sport activity stops 2 1 cen set to 1, sben dont care < 700 ms* cen read back as 1 1 2 cen reset to 0, sben reset to 0 < 150 ns* cen read back as 0 2c 1 cen set to 1, sben dont care < 30 ns* cen read back as 1 1 2c cen reset to 0, sben set to 1 < 120 ns* cen read back as 0 2 2c cen reset to 0, sben reset to 0 < 700 ms* none 2c 2 cen reset to 0, sben set to 1 < 30 ns* none 2[c]** 3[c]** dsp executes idle instruction none none 3[c]** 2[c]** dsp stops executing idle none none 2[c]** 4[c]** see power state 4 paragraph see ps4 par. pwdack pin hi 4[c]** 2[c]** see power state 4 paragraph < 7 m s pwdack pin lo 2[c]** 5[c]** see power state 5 paragraph see ps5 par. pwdack pin hi 5[c]** 2[c]** see power state 5 paragraph > 280 m s pwdack pin lo * *delay will be increased by 140 ms if the AD1801 has not yet autocalibrated itself. autocalibration is executed the first time the AD1801 transitions to power state 1 after a hard reset, i.e., a reset initiated by either the reset pin or reset pin. if the transition to power state 1 is aborted before it is completed (by resetting cen to 0), autocalibration is postponed until the next transition to power state 1. however, once autocalibration is actually b egun, which occurs at the end of the nominal transition to power state 1, it cannot be interrupted and attempts to abort the transition will be ignored until autoca libration has been completed. **power states 3, 4 and 5 can be entered only from power state 2. power states 3c, 4c and 5c can be entered only from power sta te 2c.
AD1801 C47C rev. 0 2. the dsp core looks for the presence of an external serial eeprom. using software, it looks to see whether the eeprom data and clock signals are tied together; if so, this identifies an adi test mode configuration. if the eeprom data and clock signals are independent, the dsp will typi- cally attempt to read the eeprom contents as slowly as possible, in order to minimize power. in pcmcia mode, the dsp core reads the entire eeprom contents into the cis ram and/or dsp data memory, un- less some of the eeprom data is program memory patch code. in pcmcia mode, the dsp must write 1 to the rdy bit in the dsp control register in order to notify the host that the cis memory is initialized. in isa pnp mode, the dsp core reads the first 64 bytes and writes to 0x000 through 0x03f in its i/o space, which is the start of the 512 byte cis memory. (the first byte, the first pnp identifier, must be written to the cis ram within 1 ms after system reset. the remaining eight pnp identifi ers must be written to the cis ram at a rate of one every 2 ms, or faster.) after writing the first 64 bytes of the cis memory, the dsp core typically computes a checksum or executes some other error detection algorithm. it then resumes reading the remaining contents of the eeprom into dsp data memory, unless some of the eeprom data is program memory patch code. if some of the eeprom data is program memory patch code, these instructions are written to the dsp core program memory, typically to address 0x1000. the end of the pro- gram memory rom (from which the dsp is still executing instructions) then jumps to 0x1000 and starts to execute the instructions that were just loaded. the instructions starting at 0x1000 can include writes to various AD1801 specific control bits in the dsp i/o map, including the fp1dbw and fp2dbw bits in the dsp control register which config- ure the pcmcia function port data bus widths, as well as the intp1 and intp2 bits in the default interrupt select register which configures the pcmcia function 1 and 2 interrupt polarities. actions are taken to put the AD1801 into a state that consumes as little power as possible, includ- ing full codec power-down. the code then generally settles into a loop, awaiting action from the host cpu. the dsp may enter an intermittent idle state and the eeprom will go into sleep mode. 3. by this time, the host system is coming alive. if the AD1801 is being used in an isa pnp application, the AD1801 will be configured (irq channels and isa base address) by the pnp bios routines. if the AD1801 is being used in a pcmcia application, it will be configured (irq channels and isa base address) by the pcmcia card and socket services driver. either the pnp bios or the pcmcia card and socket services also writes to the AD1801 logical device bit to en- able the AD1801. 4. the AD1801 host driver software then writes to the AD1801 pc i/o mapped registers to set up the dsp core idma controller to download the modem data pump software to the dsp core program memory. the host writes rws = 1 (in the internal dma control register) to enable write ac- cess. it also writes type = 0 (in the internal dma control register) to select program memory accesses. it then pro- grams the start address in dsp core program memory for the download (the code to be downloaded must have been linked to this absolute address) by writing this address to the ma[13:0] bit field in the internal dma control register. the host then writes the actual data (adsp-2181 instruc- tions) to the memory data output register. for program memory downloads, two 16-bit writes are required for each 24-bit program m emory word. note that the idma con- troller auto- increments the dsp program memory address following each 24-bit transfer during program memory downloads. 5. the dsp core is still awaiting action from the host cpu. there are two ways the host can notify the dsp that program memory download has been completed. either the dsp can poll a semaphore bit in its data memory (which the host can write using the same download procedure as described in 4, above, but using type = 1 to reach dsp data memory) or the host can interrupt the dsp. whether through polling a semaphore bit or through an interrupt, the dsp then jumps to the first valid instruction in the newly downloaded pro- gram memory and starts to function as a modem. note that along the way, the dsp must manage its program memory address space, i.e., it must swap out the boot rom and replace it with program memory ram. this is accomplished by resetting pmovlay to 0. AD1801 interface to smc91c94 addr sa [11:0] cs1 ce1,ce2 iois16 reg t s3 t h3 t s4 t h4 t s1 t h1 t s2 t h2 t pd1 t pd2 t pd3 t pd4 iowr,iord inpack extwr,extrd figure 13. AD1801 interface to the smc91c94 table xiv. timing parameters min typ max units ce1/ce2 from ior / iow rising (t h1 )20 ns ce1 / ce2 before ior / iow falling (t s1 )5 ns reg from ior / iow rising (t h2 )0ns reg before ior / iow falling (t s2 )5ns sa[11:0] from ior / iow rising (t h3 )20ns sa[11:0] before ior / iow falling (t s3 )70ns cs1 from ior / iow rising (t h4 )22ns cs1 before ior / iow falling (t s4 )45ns extwr falling from iow falling (t pd1 )215ns extrd falling from ior falling (t pd2 )215ns extwr rising from iow falling (t pd3 )215ns extrd rising from ior rising (t pd4 )215ns
AD1801 C48C rev. 0 AD1801 generated signal explanation: cs1 and cs2 are combinational decodes of the address lines only; they do not include reg , ce1 or ce2 . extwr and extrd , when enabled in strobe mode, are the following functions: extwr = iow + reg + ce1 extrd = ior + reg + ce1 iois16 is a combinational decode of the sa[11:0] wires without cs1 , cs2 , or reg . inpack is asserted during reads only, and depends on ior , sa[11:0], cs1 , and reg . it does not depend on cs2 . to access the external pcmcia functions, the AD1801 must operate in pcmcia mode. the smc chip may operate in either pcmcia or isa mode; isa mode is desired because the smcs cor and csr registers do not need to be programmed in isa mode. isa mode connections: 1. connect sa[3:0] to the smcs a[3:0]. this provides the register indexing. 2. the smc must have a hard coded base address (from either pins or eeprom). wire the remaining a[15:4] bits to gnd and v dd to match the hardcoded base address. 3. connect the AD1801 cs1 output to the smcs aen input. reg is the corresponding pcmcia signal; however, the timing for reg will violate the requirements of the smcs aen input. therefore reg is included in the extwr and extrd signals instead. 4. connect the smcs sbhe pin to the bus ce2 pin. 5. connect the smcs iow pin to the AD1801s extwr pin (pin 82, called irq15/vtcl2/ extwr ). 6. connect the smcs ior pin to the AD1801s extrd pin (pin 94, called irq3/vtcl1/ extrd ). before the AD1801s cor1 or cor2 is programmed, set the AD1801 into strobe mode by writing to the interrupt select register (dsp location 0x204). writing bit 13 turns on strobe mode, enabling extrd and extwr to replace vctl1 and vctl2. setting strobe mode in isa mode has no effect. following this setup, the timing is as follows: t setup [ cs1 before extrd / extwr falling] = 45 ns + 2 ns = 47 ns t hold [ cs1 from extrd / extwr rising] = 22 ns C 15 ns = 7 ns reg cs1 ce1 ce2 we sa[11:0] d[15:0] a[15,8:0] d[15:0] a9 reg ce1 ce2 oe we reset iow ior smc91c94 d[15:0] reg cs1 ce1 ce2 oe we 87 10 0 99 10 3 10 2 82 94 84 98 oe rs1 extwr extrd AD1801 sa[11:0] figure 14. smc91c94 interface to AD1801 pcmcia mode ce2 sa[11:0] d[15:0] a[3:0] d[15:0] aen intro memr sbhe reset iow ior smc91c94 d[15:0] cs1 ce2 int1 87 99 10 1 82 94 84 rs1 extwr extrd AD1801 sa[11:0] a[9:8] a[19:10,7:4]] figure 15. smc91c94 interface to AD1801 isa mode
AD1801 C49C rev. 0 application circuits v ref 10 m f 0.1 m f 12 6 figure 16. v ref bypassing 1.0nf msf 13 figure 17. monitor speaker filter 1 m f filt 1 figure 18. antialias filter connection 20C64pf 20C64pf xtali xtalo 16.9344 mhz 49 48 figure 19. crystal circuit cmout 10 m f 0.1 m f 12 5 figure 20. cmout bypassing if the target application requires any current from the cmout pin (i.e., more than a few microamps), the circuit in figure 20 (or its equivalent) must be used. the cmout output on the AD1801 cannot source/sink current directly without compro- mising analog performance. cmout 10 m f 0.1 m f 12 5 1/2 ad820 cmbuf figure 21. buffered reference circuit mspkr 100 m f 11 figure 22. monitor speaker connection mic cmout cmbuf c r 1 5k v 1 m f r 2 electret condenser microphone input 0.33 m f 1/2 ssm2135 or ad820 1/2 ad820 12 3 12 5 figure 23. phantom power mic circuit xmitn 1 m f 1 m f 6 5 to daa transmit negative differential input to daa transmit positive differential input xmitp figure 24. daa transmit circuit rcvp 1 m f 3 from daa receive single-ended output 1nf npo 470 v rcvn 4 1 m f figure 25. daa single-ended receive circuit rcvp 1 m f 3 from daa receive positive differential output from daa receive negative differential output 1nf npo 470 v 1nf npo rcvn 1 m f 4 1nf npo 470 v figure 26. daa differential receive circuit hspkrp 1 m f 1 m f 8 9 to handset speaker negative differential input to handset speaker positive differential input hspkrn figure 27. handset speaker circuit lin 1 m f line input 1nf npo 1k v 124 figure 28. line input circuitry
AD1801 C50C rev. 0 lout headphone output 47k v 68pf npo 20k v 20k v 220 m f 1/2 op279 2 12 5 cmout figure 29. headphone output circuitry note: due to the nature of the sram process used to fabricate the AD1801, the digital and analog supplies for the device must be derived from the same source. 24c04 a0 2 3 4 7 8 1 a1 a2 vss vcc test scl sda 22k v 43 42 sck sdata AD1801 5 6 figure 30. serial eeprom (two wire) circuit design guidelines the analog and digital power pins on the AD1801 have to be powered by the same supply to make sure that the analog power pins are at the same dc potential as the digital power pins. other- wise substrate currents inside the AD1801 could exceed safe limits and the device could be permanently damaged. in view of this, it is recommended that the AD1801 be located over one and the same power plane and each AD1801 power pin (dv dd and av dd ) be connected to that power plane. other digital devices on the pcb (at least ones driving AD1801 digital in- puts) would typically be connected to this same power plane. it is important that a low impedance, well bypassed power source drive this power plane to reduce the chance of any dsp code dependent noise appearing on the AD1801 analog signals. the isa/pcmcia bus +5 v supply should suffice for this purpose. in addition to bypassing each AD1801 supply pin, it is recom- mended that an array of 0.001 m f, 1 m f ceramic and 10 m f tantalum capacitors be connected between the power plane and ground where power enters the pcb. to minimize the digital ground currents flowing through the analog area, it is recommended that two ground planes be used for the AD1801, one for the digital half of the AD1801 plus other digital circuitry (digital ground plane), and the other for the analog half of the AD1801 plus any other analog circuitry (analog ground plane). this is shown in figure 31. the analog and digital ground planes should only be tied together (mecca), at the point where the supply enters the pcb. instead of con- necting the two ground planes directly (with a trace) on proto- type pcbs, it is recommended that this connection be made with a wire. this provides the flexibility to connect the two ground planes through a ferrite bead (which increases the isola- tion between the analog and digital circuitry), which may be desirable in some systems. care should be taken to provide as clean supplies as possible to the AD1801. at a minimum, an array of 10 m f, 0.1 m f and 0.01 m f capacitors should be used to filter the supply used to power the AD1801 where it enters the pcb. a combination of ferrite beads and capacitors can also be used to filter the supply, but care should be observed when doing this, since a particular combination of values, along with the power line supplying the pcb, may form a high q circuit that could produce undesirable ringing of the supplies. as a general rule, regulating the +12 v available on the isa bus may provide the cleanest supplies for the analog circuitry. if a regulator is used, it should be located close to where the unregulated voltage enters the pcb, at mecca ground. in addition to having the amplifiers that perform signal condi- tioning on the daa input also perform antialias filtering, it is recommended that the user build their first system with addi- tional rc antialias circuitry between the daa amplifiers and the daa adc input as shown in figures 25 and 26. in addition to providing residual antialias filtering, the resistors isolate the daa amplifiers from the switched capacitor daa adc inputs. these components may be removed if performance testing yields satisfactory results with the components not installed. the audio inputs (mic and lin) should not need an antialias filter in addition to what is provided by the amplifiers that drive those inputs. installing such rc filters on the audio inputs, however, will only help improve the performance of the audio channels, especially in a noisy environment. to ensure the best performance, the AD1801 bypass capacitors should be located as close to the AD1801 as possible. the fol- lowing capacitors should be located as close to the AD1801 as possible. note that the positive side (preferably also the ground side) of the supply bypass capacitors should be connected di- rectly to the pin they are bypassing (i.e., not connected through the power plane). this list is in the order of importance with the capacitors that should be located closest listed first: 1. 0.1 m f ceramic capacitors bypassing v ref and cmout. 2. 0.1 m f ceramic capacitors on the voltage supply pins and the 22 pf capacitors on the crystal i/o pins. 3. any antialias filter capacitors and ac coupling capacitors that may be needed on the adc inputs and the 1 nf ceramic capacitor on the msf pin. 4. 10 m f tantalum capacitors bypassing v ref and cmout and the 1 m f tantalum capacitor connected to the filt pin. 5. input and output ac coupling capacitors not mentioned above do not need to be located close to the AD1801.
AD1801 C51C rev. 0 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 56 57 58 59 55 50 51 52 53 54 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 100 hspkrn lout rcvp rcvn xmitp xmitn hspkrp mspkr agnd msf av dd av dd agnd pcm_ isa pnp_ std reset reset ereset dv dd dv dd elin eint eclk ebr ee ebg ems io7 elout io6 io5 io3 io2 io4 filt agnd av dd agnd sd7 sd8 sd9 dgnd dgnd ior iow iochrdy/ wait irq4/ inpk irq3/vctl1/ extrd irq5/ chg irq7/ spkr dv dd irq9/ ireq irq10/ cs 1 dv dd dgnd irq11/ rs 1 irq12/pd1 iocs16/iois16 sd0 sd1 dv dd dgnd sd2 sd5 dv dd dgnd irq15/vctl2/ extwr sd3 sd4 sd6 sd10 aen/ reg sa13/ we sa14/int1 sa1 5/ ce1 sbhe/ce2 dv dd cmout trs sa12/ oe agnd v ref lin mic tms tdi tck tdo dgnd sa0 sa1 sa2 sa3 sa4 sa5 sa6 av dd sa7 sa8 sa9 sa10 sa11 sd15 sd14 io0 sen sdata sck dgnd dv dd ring dgnd xtali dv dd pwdack dr/int2 dt/pd2 sclk dgnd dv dd sd13 sd12 sd11 io1 pdw xtalo rfs/ cs 2 tfs/ rs 2 AD1801 analog ground plane digital ground plane figure 31. AD1801 ground planes
C52C c2814C1C4/98 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 128-lead pqfp (s-128a) 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) top view (pins down) 1 38 39 65 64 102 128 103 0.020 (0.50) bsc 0.685 (17.40) 0.677 (17.20) 0.669 (17.00) 0.791 (20.10) 0.767 (20.00) 0.783 (19.90) 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) 0.921 (23.40) 0.913 (23.20) 0.906 (23.00) seating plane 0.134 (3.40) max 0.041 (1.03) 0.035 (0.88) 0.031 (0.78) 0.003 (0.08) max 0.010 (0.25) min 0.110 (2.80) 0.106 (2.70) 0.102 (2.60) 128-lead tqfp (st-128) top view (pins down) 1 38 39 65 64 102 128 103 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) 0.551 (14.00) bsc 0.630 (16.00) bsc 0.020 (0.50) bsc seating plane 0.063 (1.60) typ 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.003 (0.08) max 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.40) 0.018 (1.35) 0.866 (22.00) bsc 0.787 (20.00) bsc AD1801 rev. 0

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